SMJ626162 Datasheet, PDF (3/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

operation (continued)
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
Table 1. Basic Command Truth Table^†
COMMAND
STATE OF
BANK(S)
CS
RAS CAS
W
A11 A10
Mode register set
T = deac
B = deac
L
L
L
L
X
X
Bank deactivate (precharge)
X
L
L
H
L
BS
L
Deactivate all banks
X
L
L
H
L
X
H
Bank activate/row-address entry
SB = deac L
L
H
H
BS
V
Column-address entry / write operation SB = actv
L
H
L
L
BS
L
Column-address entry / write operation
with auto-deactivate
SB = actv
L
H
L
L
BS
H
Column-address entry/read operation
SB = actv
L
H
L
H
BS
L
Column-address entry/read operation
with auto-deactivate
SB = actv
L
H
L
H
BS
H
No operation
X
L
H
H
H
X
X
Control-input inhibit / no operation
X
H
X
X
X
X
X
Autorefresh‡
T = deac
B = deac
L
L
L
H
X
X
† _{For execution of these commands on cycle n, one of the following must be true:}
– CKE (n–1) must be high
– tCESP must be satisfied for power-down exit
– tCES and nCLE must be satisfied for clock-suspend exit. DQMx (n) is irrelevant.
‡ _{Autorefresh entry requires that all banks be deactivated or be in an idle state prior to the command entry.}
Legend:
n = CLK cycle number
L = Logic low
H = Logic high
X = Don’t care, either logic low or logic high
V = Valid
T = Bank T
B = Bank B
actv = Activated
deac = Deactivated
BS = Logic high to select bank T; logic low to select bank B
SB = Bank selected by A11 at cycle n
A9 – A0 MNEMONIC
A9 = V
A8 – A7 = 0
A6 – A0 = V
X
X
V
V
MRS
DEAC
DCAB
ACTV
WRT
V
WRT-P
V
READ
V
READ-P
X
NOOP
X
DESL
X
REFR
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