SMJ626162 Datasheet, PDF (35/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

CLK
DQ0 – DQ7
DQML
DQ8 – DQ15
DQMU
ACTV B
ACTV T
READ B
READ T
READ B
READ T
READ B
a
b
c
d
e
f
Hi-Z
RAS
CAS
W
A10
R0
R1
A11
A0 – A9
R0
CS
R1
C0
C1
C2
C3
C4
CKE
BURST
TYPE
BANK
ROW
BURST CYCLE†
(D/Q) (B/ T ) ADDR
a
b
c
d
e
f
g
h
Q
T
R0
C0 C0 + 1
Q
B
R1
C1
C1+1
Q
T
R0
C2
C1+1
Q
B
R1
C3
C3+ 1
† _{Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 4).}
Figure 30. Data Mask With Byte Control (read latency = 3, burst length = 2)