SMJ626162 Datasheet, PDF (2/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
description (continued)
The SDRAM employs state-of-the-art technology for high performance, reliability, and low power requirements.
All inputs and outputs are synchronized with the CLK input to simplify system design and enhance use with
high-speed microprocessors and caches.
The SMJ626162 SDRAM is available in a 50-lead, 650-mil-wide ceramic dual flatpack (HKD suffix).
functional block diagram
CLK
CKE
CS
DQMx
RAS
CAS
W
A0–A11
AND
12
Control
Array Bank T
Array Bank B
DQ
Buffer
DQ0–DQ15
16
Mode Register
operation
All inputs to the ’626162 SDRAM are latched on the rising edge of the system (synchronous) clock. The outputs,
DQ0–DQ15, are also referenced to the rising edge of CLK. The ’626162 has two banks that are accessed
independently; however, a bank must be activated before it can be accessed (read from or written to). Refresh
cycles refresh both banks alternately.
Five basic commands or functions control most operations of the ’626162:
D Bank-activate/row-address entry
D Column-address entry/write operation
D Column-address entry/read operation
D Bank-deactivate
D Autorefresh
Additionally, operations can be controlled by three methods: using chip select (CS) to select/deselect the
devices, using DQMx to enable/mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend (or
gate) the CLK input. The device contains a mode register that must be programmed for proper operation.
Table 1, Table 2, and Table 3 show the various operations that are available on the ’626162. These truth tables
identify the command and/or operations and their respective mnemonics. Each truth table is followed by a
legend that explains the abbreviated symbols. An access operation refers to any read or write command in
progress at cycle n. Access operations include the cycle upon which the read or write command is entered and
all subsequent cycles through the completion of the access burst.
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