SMJ626162 Datasheet, PDF (33/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

CLK
DQ
ACTV T
WRT- P T
ACTV B
READ- P B
a
b
c
d
e
f
g
DQMx
RAS
CAS
W
A10
R0
R1
A11
A0 – A9
R0
R1
C0
C1
CS
CKE
BURST
TYPE
BANK
ROW
BURST CYCLE ^†
(D/Q) (B/ T ) ADDR
a
b
c
d
e
f
g
h
D
T
R0
C0 C0 + 1 C0 + 2 C0 + 3
Q
B
R1
C1 C1 + 1 C1 + 2 C1 + 3
† _{Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).}
NOTE A: This example illustrates minimum nCWL for the ’626162-15 at 66 MHz.
Figure 28. Write-Burst Bank T, Read-Burst Bank B With Automatic Deactivate (read latency = 3, burst length = 4)