SMJ626162 Datasheet, PDF (17/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
ac timing requirements^†‡ (continued)
’626162-12 ’626162-15 ’626162-20
UNIT
MIN MAX MIN MAX MIN MAX
tAPR
Final data out of READ-P operation to ACTV, MRS, or REFR
command
tRP + (nEP × tCK)
ns
tAPW Final data in of WRT-P operation to ACTV, MRS, or REFR command
tRP + tCK
ns
tRWL Final data in to DEAC or DCAB command
24
30
40
ns
tRRD ACTV command for one bank to ACTV command for the other bank
24
30
40
ns
tT
Transition time, all inputs (see Note 13)
1
5
1
5
1
5 ns
tREF Refresh interval
32
32
32 ms
† _{See Parameter Measurement Information for load circuits.}
‡ _{All references are made to the rising transition of CLK unless otherwise noted.}
NOTE 13: Transition time (rise and fall) should be a minimum of 1 ns and a maximum of 5 ns measured between VIH MIN and VIL MAX. This is
ensured by design but not tested.
clock timing requirements^‡§
’626162-12 ’626162-15 ’626162-20
MIN MAX MIN MAX MIN MAX ^UNIT§
nEP
Final data out to DEAC or ^{Read latency = 2}
DCAB command
Read latency = 3
–1
–1
–1
cycles
–2
–2
–2
nHZP
DEAC or DCAB interrupt of _{Read latency = 2}
data-out burst to DQ in the
high-impedance state
Read latency = 3
2
2
2
cycles
3
3
3
nCCD
READ or WRT command to interrupting READ, WRT, DEAC, or DCAB
command
1
1
1
cycles
nCWL
nWCD
nDID
nDOD
nCLE
Final data in to READ or WRT command in either bank
WRT command to first data in
ENBL or MASK command to data in
ENBL or MASK command to data out
HOLD command to suspended CLK edge;
HOLD operation exit to entry of any command
1
1
1
cycles
0
0
0
0
0
0 cycles
0
0
0
0
0
0 cycles
2
2
2
2
2
2 cycles
1
1
1
1
1
1 cycles
nRSA MRS command to ACTV, REFR, or MRS command
2
2
2
cycles
nCDD DESL command to control input inhibit
0
0
0
0
0
0 cycles
‡ _{All references are made to the rising transition of CLK unless otherwise noted.}
§ _{A CLK cycle can be considered as contributing to a timing requirement for those parameters defined in cycle units only when not gated by CKE}
(those CLK cycles occurring during the time when CKE is asserted low).
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