SMJ626162 Datasheet, PDF (10/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
CLK-suspend/power-down mode
For normal device operation, CKE must be held high to enable CLK. If CKE goes low during the execution of
a read or write operation, the DQ bus occurring at the immediate next rising edge of CLK is frozen at its current
state. No further inputs are accepted until CKE returns high; this is known as a CLK-suspend operation, and
its execution is denoted as a HOLD command. The device resumes operation from the point at which it was
placed in suspension, beginning with the second rising edge of CLK after CKE returns high.
If CKE is brought low when no read or write command is in progress, the device enters the power-down mode.
If both banks are deactivated when the power-down mode is entered, power consumption is reduced to the
minimum. Power-down mode can be used during row-active or autorefresh periods to reduce input-buffer
power. After power-down mode is entered, no further inputs are accepted until CKE returns high. To ensure that
data in the device remains valid, the power-down mode must be exited periodically to meet the requirements
described earlier for device refresh. When exiting power-down mode, new commands can be entered on the
first CLK edge after CKE returns high, provided that the setup time (t_CESP) is satisfied. Table 2 shows the
command configuration for a CLK-suspend/power-down operation; Figure 17, Figure 18, and Figure 35 show
examples of the procedure.
interrupted bursts
A read burst or write burst can be interrupted before the burst sequence has been completed with no adverse
effects to the operation. This is accomplished by entering certain superseding commands as listed in Table 7
and Table 8, provided that all timing requirements are met. A DEAC command is considered an interrupt only
if it is issued to the same bank as the preceding READ or WRT command. The interruption of a READ-P or a
WRT-P operation is not supported.
INTERRUPTING
COMMAND
READ, READ-P
WRT, WRT-P
DEAC, DCAB
Table 7. Read-Burst Interruption
EFFECT OR NOTE ON USE DURING READ BURST
Current output cycles continue until the programmed latency from the superseding READ (READ-P) command is met
and new output cycles begin (see Figure 2).
The WRT (WRT-P) command immediately supersedes the read burst in progress. To avoid data contention, DQMx must
be held high before the WRT (WRT-P) command to mask output of the read burst on cycles (nCCD–1), nCCD, and
(nCCD+1), assuming that there is any output on these cycles (see Figure 3).
The DQ bus is in the high-impedance state when nHZP cycles are satisfied or when the read burst completes, whichever
occurs first (see Figure 4).
CLK
nCCD = 1 Cycle
READ Command
at Column Address C0
Interrupting
READ Command
at Column Address C1
DQ
Output Burst for the
Interrupting READ
Command Begins Here
C0
C1
C1 + 1
NOTE A: For this example, assume read latency = 3 and burst length = 4.
Figure 2. Read Burst Interrupted by Read Command
C1 + 2
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