SMJ626162 Datasheet, PDF (27/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

CLK
DQ
DQMx
RAS
CAS
W
A10
A11
A0 – A9
CS
CKE
ACTV T READ T
R0
R0
C0
WRT-P T
abcde f gh
i
j
k
l mn o p
C1
BURST
TYPE
BANK
ROW
BURST CYCLE†
(D/Q) (B/ T ) ADDR a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
Q
T
R0
C0 C0 + 1 C0 + 2 C0 + 3 C0 + 4 C0 + 5 C0 + 6 C0 + 7
D
T
R0
C1 C1 + 1 C1 + 2
† _{Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 6).}
NOTE A: This example illustrates minimum tRCD for the ’626162-15 at 66 MHz.
C1 + 3
C1 + 4
C1 + 5
C1 + 6
C1 + 7
Figure 22. Read-Write Burst With Automatic Deactivate (read latency = 3, burst length = 8)