SMJ626162 Datasheet, PDF (31/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

CLK
DQ
DQMx
ACTV B
ACTV T
READ B
READ T
READ B
READ T
READ B
a
b
c
d
e
f
RAS
CAS
W
A10
R0
R1
A11
A0 – A9
R0
R1
C0
C1
C2
C3
C4
CS
CKE
BURST
TYPE
BANK
ROW
BURST CYCLE ^†
(D/Q) (B/ T ) ADDR
a
b
c
d
e
f
...
...
Q
B
R0
C0 C0 + 1
Q
T
R1
C1 C1 + 1
Q
B
R0
C2 C2 + 1
.
...
...
...
...
† _{Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see Table 4).}
Figure 26. Two-Bank Column-Interleaving Read Bursts (read latency = 3, burst length = 2)