SMJ626162 Datasheet, PDF (18/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
The ac timing measurements are based on signal rise and fall times equal to 1 ns (t_T = 1 ns) and a midpoint
reference level of 1.4 V for LVTTL. For signal rise and fall times greater than 1 ns, the reference level is changed
to V_IH MIN and V_IL MAX instead of the midpoint level. All specifications referring to READ commands are also
valid for READ-P commands unless otherwise noted. All specifications referring to WRT commands are also
valid for WRT-P commands unless otherwise noted. All specifications referring to consecutive commands are
specified as consecutive commands for the same bank unless otherwise noted.
Tester Pin
Electronics
1.4 V
IOL
(see Note A)
50 Ω
CL = 50 pF
IOH
Output
Under
Test
NOTE A: Series termination resistors may be used on test
hardware for output impedance matching purposes.
Figure 8. LVTTL-Load Circuit
tCK
tCKH
CLK
tDS, tAS, tCS, tCES
tCKL
tT
tT
tDH, tAH, tCH, tCEH
DQ, A0–A11, CS, RAS,
CAS, W, DQMx, CKE
tT
tDS, tAS, tCS, tCES, tCESP
tDH, tAH, tCH, tCEH
DQ, A0–A11, CS, RAS,
CAS, W, DQMx, CKE
tT
Figure 9. Input-Attribute Parameters
18
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443