SMJ626162 Datasheet, PDF (38/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

CLK
DQ
DQMx
RAS
CAS
W
A10
A11
A0 – A9
CS
CKE
REFR
ACTV T
READ T
DEAC T
REFR
a
b
c
d
R0
R0
C0
BURST
TYPE
BANK
ROW
BURST CYCLE†
(D/Q) (B/ T ) ADDR
a
b
c
d
Q
T
R0
C0 C0 + 1 C0 + 2 C0 + 3
† _{Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).}
NOTE A: This example illustrates minimuim tRC, tRCD, and nEP for the ’626162-15 at 66 MHz.
Figure 33. Refresh Cycles (read latency = 3, burst length = 4)