SMJ626162 Datasheet, PDF (26/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

3
ACTV B
WRT B
READ B
DEAC B
CLK
DQ
a
b
c
d
DQMx
RAS
CAS
W
A10
R0
A11
A0 – A9
R0
C0
C1
CS
CKE
BURST
TYPE
BANK
ROW
BURST CYCLE†
(D/Q) (B/ T ) ADDR
a
b
c
d
D
B
R0
C0 C0 + 1
Q
B
R0
C1 C1 + 1
† _{Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 4).}
NOTE A: This example illustrates minimum tRCD and nEP for the ’626162-15 at 66 MHz.
Figure 21. Write-Read Burst (read latency = 3, burst length = 2)