SMJ626162 Datasheet, PDF (39/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

CLK
DQ
DQMx
RAS
CAS
W
A10
A11
A0 – A9
CS
CKE
DCAB
MRS
ACTV B
WRT-P B
a
b
c
d
R0
See Note B
See Note B
R0
C0
See Note B
BURST
TYPE
BANK
ROW
BURST CYCLE†
(D/Q) (B/ T ) ADDR
a
b
c
d
D
B
R0
C0 C0 + 1 C0 + 2 C0 + 3
† _{Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).}
NOTES: A. This example illustrates minimum tRP, nRSA, and tRCD for the ’626162-15 at 66 MHz.
B. See Figure 1.
Figure 34. Set Mode Register (deactivate all, set mode register, write burst with automatic deactivate)
(read latency = 3, burst length = 4)