SMJ626162 Datasheet, PDF (15/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (see Note 2)
PARAMETER
VOH
VOL
II
IO
High-level output
voltage
Low-level output
voltage
Input current
(leakage)
Output current
(leakage)
TEST CONDITIONS
IOH = –2 mA
IOL = 2 mA
0 V ≤ VI ≤ VCC,
All other pins = 0 V to VCC
0 V ≤ VO ≤ VCCQ, Output disabled
’626162-12 ’626162-15 ’626162-20
UNIT
MIN MAX MIN MAX MIN MAX
2.4
2.4
2.4
V
0.4
0.4
0.4 V
±10
±10
±10 µA
±10
±10
±10 µA
Burst length = 1,
ICC1
Average read or
write current
tRC ≥ tRC MIN,
IOH/IOL = 0 mA,
One bank activated
Read latency = 2
Read latency = 3
85
100
75
95
70
mA
85
(see Note 3)
ICC2P
ICC2PS
Precharge standby
current in
power-down mode
v ^{CKE ≤ VIL MAX, tCK = MIN (see Note 4)}
CKE and CLK VIL MAX,
tCK = ∞ (see Note 5)
2
2
2
2
2
mA
2
ICC2N ^{Precharge standby} CKE ≥ VIH MIN, tCK = MIN (see Note 4)
40
35
30
current in
ICC2NS
nonpower-down
mode
CKE ≥ VIH MIN, CLK ≤ VIL MAX,
tCK = ∞ (see Note 5)
mA
2
2
2
ICC3P
ICC3PS
Active standby
current in
power-down mode
CKE ≤ VIL MAX, tCK = MIN
One bank activated (see Note 4)
CKE and CLK ≤ VILMAX, tCK = ∞
One bank activated (see Note 5)
10
10
10
mA
10
10
10
ICC3N
ICC3NS
Active standby
current in
nonpower-down
mode
ICC4
Burst current
CKE ≥ VIH MIN, tCK = MIN
One bank activated (see Note 4)
CKE ≥ VIH MIN, CLK ≤ VIL MAX,
tCK = ∞, One bank activated (see Note 5)
Continuous burst,
IOH/IOL = 0 mA,
All banks activated,
nCCD = one cycle
(see Note 6)
Read latency = 2
Read latency = 3
55
45
40
mA
15
15
15
165
130
110
mA
210
175
150
ICC5
Autorefresh
tRC ≥ tRC MIN
Read latency = 2
Read latency = 3
120
100
120
100
80
mA
80
NOTES:
2. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
3. Control and address inputs change state twice during tRC.
4. Control and address inputs change state once every 2 × tCK.
5. Control and address inputs do not change state (stable).
6. Control and address inputs change state once every cycle.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
15