GC5018 Datasheet, PDF (84/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
Register name: RAGC3_INTEGINVL_LSB
BIT 15
0
0
0
BIT 7
0
0
0
Address: 0x2B
integ_interval_3(15:8)
0
0
0
integ_interval_3(7:0)
0
0
0
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BIT 8
0
0
BIT 0
0
0
integ_interval_3(15:0) : The LSBs of the integration time for receive AGC 3
4.4.4.45 RAGC3_INTEGINVL_MSB Register
Register name: RAGC3_INTEGINVL_MSB
BIT 15
0
0
0
BIT 7
0
0
0
Address: 0x2C
ragc_update_3(7:0)
0
0
0
integ_interval_3(23:16)
0
0
0
BIT 8
0
0
BIT 0
0
0
ragc_update_3(7:0) : Sets the number of receive AGC updates per sync event (0x00 is infinite).
integ_interval_3(23:16) : The MSBs of the integration time for receive AGC 3
4.4.4.46 RAGC3_CONFIG0 Register
Register name: RAGC3_CONFIG0
BIT 15
0
0
0
BIT 7
hp_corner_3(2:0)
0
0
0
Address: 0x2D
ragc_sync_delay_3(7:0)
0
0
0
0
acc_shift_3(4:0)
0
0
0
0
BIT 8
0
BIT 0
0
ragc_sync_delay_3(7:0) : The input sync to the receive AGC block is delayed by this value of samples.
hp_corner_3(2:0) : This sets the corner frequency of the High Pass filter. Larger values result in higher
corner frequencies.
acc_shift_3(4:0) : Selects the integrated power measurements result bits to be used as the error lookup
table address. A larger number means fewer samples will have to be integrated to achieve
the same result.
4.4.4.47 RAGC3_CONFIG1 Register
Register name: RAGC3_CONFIG1
Address: 0x2E
BIT 15
acc_offset_3(5:0)
0
0
0
0
0
0
84
GC5018 GENERAL CONTROL
BIT 8
err_shift_3(4:3)
0
0