GC5018 Datasheet, PDF (112/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
6.4 DC CHARACTERISTICS
–40°C to 85°C case (unless otherwise noted)
PARAMETER
V_IL
V_IH
V_OL
V_OH
|I_PU|
|I_PD|
|I_IN|
I_CCQ
C_IN
C_BI
Voltage input low
Voltage input high
Voltage output low (I_OL = 2 mA)⁽¹⁾
Voltage output high (I_OH = –2 mA)⁽¹⁾
Pullup current (V_IN = 0 V) (tdi, tms, trst_n, ce_n, wr_n, rd_n, reset_n ) (nominal 20 µA)⁽¹⁾
Pulldown current (V_IN = VDDS) (all other inputs and bidirectionals) (nominal 20 µA) ⁽¹⁾
Leakage current (V_IN = 0V or VDDS), Outputs in 3-state condition ⁽¹⁾
Quiescent supply current, IDVDD or IVDDS (V_IN = 0 for pads with pulldowns,
V_IN = VDDS for inputs with pullups) ⁽¹⁾
Capacitance for inputs⁽²⁾
Capacitance for bidirectionals⁽²⁾
www.ti.com
VDDS=3 V to 3.6 V
MIN
MAX
0.8
2.0
0.5
2.4
VDDS
5
35
5
35
20
8
UNIT
V
V
V
V
µA
µA
µA
mA
Typical 5 Typical 5 pF
Typical 5 Typical 5 pF
(1) Each part is tested at TBDoC case temperature for the given specification. Lots are sample tested at -40oC.
(2) Controlled by design and process and not directly tested.
6.5 AC TIMING CHARACTERISTICS⁽³⁾⁽⁴⁾
–40°C to 85°C case supplies across recommended range (unless otherwise noted)
PARAMETER
F_CK
Clock frequency (adcclk_a/b/c/d, rxclk)⁽¹⁾
t_CKL
Clock low period (below V_IL) (adcclk_a/b/c/d, rxclk)⁽¹⁾
t_CKH
Clock high period (above V_IH) (adcclk_a/b/c/d, rxclk)⁽¹⁾
t_RF
Clock rise and fall times (V_IL to V_IH) (adcclk_a/b/c/d, rxclk)⁽²⁾
Input setup (rxsync_a/b/c/d) before rxclk rises⁽¹⁾
t_SU
Input setup (rxin_a/b/c/d_[0-15] ) before rxclk rises (adc fifo blocks bypassed)⁽¹⁾
Input setup (rxin_a/b/c/d_[0-15] ) before adcclk_a/b/c/d rises (adc fifo blocks enabled)⁽¹⁾
Input hold (rxsync_a/b/c/d) after rxclk rises⁽¹⁾
t_HD
Input hold (rxin_a/b/c/d_[0-15] ) after rxclk rises (adc fifo blocks bypassed)⁽¹⁾
Input hold (rxin_ a/b/c/d_[0-15] ) after adcclk_a/b/c/d rises (adc fifo blocks enabled)⁽¹⁾
t_DLY
Data output delay (rx_sync_out_[0-7], rxout_[0-7]_a/b/c/d, rxclk_out, rx_sync_out, dvga_[a-d]_[5-0])
after rxclk rises.⁽¹⁾
t_OHD
Data output hold (rx_sync_out_[0-7], rxout_[0-7]_a/b/c/d, rxclk_out, rx_sync_out, dvga_[a-d]_[5-0])
after rxclk rises.⁽¹⁾
F_JCK
t_JCKL
t_JCKH
t_JSU
t_JHD
t_JDLY
t_CSU
JTAG Clock frequency (tck)⁽¹⁾
JTAG Clock low period (below V_IL) (tck)⁽¹⁾
JTAG Clock high period (above V_IH) (_tck)⁽¹⁾
JTAG Input (tdi or tms) setup before tck goes high⁽¹⁾
JTAG Input (tdi or tms) hold time after tck goes high⁽¹⁾
JTAG output (tdo) delay from falling edge of tck.⁽¹⁾
Control setup during reads or writes
3 pin mode: a[5:0] valid before rd_n, wr_n or ce_n falling edge
2 pin mode: a[5:0] and wr_n valid before ce_n falling edge ⁽¹⁾
MIN MAX UNIT
160 MHz
2
ns
2
ns
2 ns
2
2
ns
2
1
2
ns
1
6.5 ns
0.5
ns
40 MHz
10
ns
10
ns
1
ns
10
ns
10
6
ns
(3) Timing is measured from the respective clock at VDDS/2 to input or output at VDDS/2. Output loading is a 50 Ω transmission line whose
delay is calibrated out.
(4) Controlled by design and process and not directly tested. Verified on initial part evaluation.
(1) Each part is tested at 90°C case temperature for the given specification. Lots are sample tested at –40°C.
(2) Recommended practice.
112 SPECIFICATIONS