GC5018 Datasheet, PDF (38/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
www.ti.com
The input data is received with a valid flag that is high when a valid sample is received. For complex data
the I and Q samples are on the same data input line and are not treated independently. An adjustment is
made for the magnitude of the I sample, and then another adjustment is made for the Q sample.
The AGC operates on UMTS and CDMA data. When in UMTS mode the I and Q data are each used to
produce the AGC level. There is no separate I path gain and Q path gain. When in CDMA mode there are
separate gain levels for the Signal and Diversity I and Q data. The I and Q for A (or the Signal ) pair is
calculated and then the I' and Q' for the B (or Diversity) pair is calculated.
There is a freeze mode for holding the accumulator at its current level. This will put the AGC in a hold
mode using the user-programmed gain along with the current gain_adjust value. To only use the user
programmed gain value as the gain, set the freeze bit and then clear the accumulator. When using the
freeze bit the full 25 bit output is sent out of the AGC block to support transferring up to 25 bits when the
AGC is disabled.
For TDD applications, freeze mode can be controlled using a sync source. This allows rxsync_a/b/c/d to
be assigned as a AGC hold signal to keep the AGC from responding during the transmit interval and run
during the receive interval. The freeze register bit is logically Ored with the freeze sync source.
The current AGC gain and state can also be optionally output with the DDCs I and Q output data by
setting the gain_mon variable. When in this mode, the top 14 bits of the current AGC gain word are
appended to the 8 bit AGC-modified I and Q output data.
Output
I
Q
Bits(17:10)
I output data
Q output data
Bits(9:4)
Bits(3:2)
Gain(23:16)
Gain(15:10)
AGC State(1:0)
Bits(1:0)
“00”
“00”
VARIABLE
agc_dblw(3:0)
agc_dabv(3:0)
agc_dzro(3:0)
agc_dsat (3:0)
agc_zero_msk(3:0)
agc_md(3:0)
agc_thresh(7:0)
agc_rnd_disable
agc_freeze
agc_clear
agc_gaina(23:0)
agc_gainb(23:0)
agc_zero_cnt(3:0)
agc_max_cnt(3:0)
agc_amax(15:0)
agc_amin(15:0)
gain_mon
PROGRAMMING
DESCRIPTION
Below threshold gain. Sets the value of gain step size Dblw (data x current gain below threshold). Ranges from
3 to 18, and maps to a 4 bit field. For example: 3 = “0000”, 4= “0001”, … 18= “1111”
Above threshold gain. Sets the value of gain step size Dabv (data x current gain above threshold). Ranges
from 3 to 18, and maps to a 4 bit field. For example: 3 = “0000”, 4= “0001”, … 18= “1111”
Zero signal gain. Sets the value of gain step size Dzro (data x current gain consistently zero). Ranges from 3 to
18, and maps to a 4 bit field. For example: 3 = “0000”, 4= “0001”, … 18= “1111”
Saturated signal gain. Sets the value of gain step size Dsat (data x current gain consistently saturated).
Ranges from 3 to 18, and maps to a 4 bit field. For example: 3 = “0000”, 4= “0001”, … 18= “1111”
Masks the lower 4 bits of signal data so as to be considered zeros.
AGC rounding. 0000= 18 bits out, 1111= 3 bits out.
AGC threshold. Compared with magnitude of 8 bits of input x gain.
AGC rounding is disabled when this bit is set.
The AGC gain adjustment updates are disable when set.
The AGC gain adjustment accumulator is cleared when set
24 bit gain word for DDC A
24 bit gain word for DDC B (in CDMA mode)
When the AGC output (input x gain) is zero value this number of times, the shoft value is changed to
agc_dzero.
When the AGC output (input x gain) is zero value this number of times, the shift value is changed to agc_dsat.
The maximum value that gain can be adjusted up to. Top 12 bits are integer, bottom 4 bits are fractional.
The minimum value that gain can be adjusted down to. Top 12 bits are integer, bottom 4 bits are fractional.
When set, combines current AGC gain with I and Q data. The 18 bit output format thus becomes:
I Portion: 8 bits of AGC’d I data - Gain(23:16) - 00
Q Portion: 8 bits of AGC’d Q data - Gain(15:10) - Status(1:0) - 00.
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RECEIVE DIGITAL SIGNAL PROCESSING