GC5018 Datasheet, PDF (43/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
Global Address 33 is the page register. Writing a 16 bit value to this register sets the page to which future
write or read operations performed. These paged-registers contain the actual parameters that configure
the chip and are accessed by writing/reading address 0 through address 31.
The global 3-state register can be used to 3-state the output drivers on the GC5018, and also includes the
capability of disabling the chip’s internal rxclk.
VARIABLE
rxclk_ena
3-state(10:0)
arst_func
PROGRAMMING
DESCRIPTION
Enables the internal rxclk when set. When cleared, the GC5018 will ignore the rxclk input signal and
hold the internal clock low.
Various output pins are forced into tristate mode when these bits are asserted. See the GBL_3-STATE
register description for pin groups to bit assignments.
When asserted, the internal datapath is held reset. The control register programming is not affected.
4.1 Microprocessor Interface Control Data, Address, and Strobes
The microprocessor control bus consists of 16 bi-directional control data lines d[15:0], 6 address lines
a[5:0], a read enable line rd_n, a write enable line wr_n, and a chip enable line ce_n. These lines usually
interface to a microprocessor or DSP chip and is intended to look like a block of memory.
The interface can be operated in a 3 pin control mode (using rd_n, wr_n and ce_n) or 2 pin control mode
(using wr_n and ce_n with rd_n always low).
4.1.1 MPU Timing Diagrams
ce_n
tREC
wr_n
rd_n
a[5:0]
d[15:0]
tCSU
tCDLY
valid data
tHIZ
tCOH
Figure 4-1. Read Operation – 3 pin control mode
GC5018 GENERAL CONTROL
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