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GC5018 Datasheet, PDF (106/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
Signal Name
Ball
dvga_d_4
P1
dvga_d_3
P4
dvga_d_2
N2
dvga_d_1
R1
dvga_d_0
N3
Type
output
output
output
output
output
Description
Digital VGA control output for rxin_d
Digital VGA control output for rxin_d
Digital VGA control output for rxin_d
Digital VGA control output for rxin_d
Digital VGA control output for rxin_d LSB
rxin_a_15
rxin_a_14
rxin_a_13
rxin_a_12
rxin_a_11
rxin_a_10
rxin_a_9
rxin_a_8
rxin_a_7
rxin_a_6
rxin_a_5
rxin_a_4
rxin_a_3
rxin_a_2
rxin_a_1
rxin_a_0
C15
input
receive input data bus a bit 15 (MSB)
B15
input
receive input data bus a
C14
input
receive input data bus a
B14
input
receive input data bus a
A16
input
receive input data bus a
A15
input
receive input data bus a
C13
input
receive input data bus a
B13
input
receive input data bus a
A14
input
receive input data bus a
C12
input
receive input data bus a
B12
input
receive input data bus a
A12
input
receive input data bus a
C11
input
receive input data bus a
B11
input
receive input data bus a
D11
input
receive input data bus a
C10
input
receive input data bus a bit 0 (LSB)
rxin_b_15
B9
rxin_b_14
D9
rxin_b_13
A9
rxin_b_12
C8
rxin_b_11
B8
rxin_b_10
D8
rxin_b_9
C7
rxin_b_8
B7
rxin_b_7
A7
rxin_b_6
B6
rxin_b_5
C6
rxin_b_4
A5
rxin_b_3
B5
rxin_b_2
C5
rxin_b_1
A4
rxin_b_0
B4
rxin_c_15
A2
rxin_c_14
B3
rxin_c_13
B2
rxin_c_12
C3
rxin_c_11
C2
rxin_c_10
A1
rxin_c_9
D3
rxin_c_8
D2
rxin_c_7
B1
106 GC5018 PINS
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
receive input data bus b bit 15 (MSB)
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b bit 0 (LSB)
receive input data bus c bit 15 (MSB), test bus bit 17
receive input data bus c bit 14, test bus bit 16
receive input data bus c bit 13, test bus bit 15
receive input data bus c bit 12, test bus bit 14
receive input data bus c bit 11, test bus bit 13
receive input data bus c bit 10, test bus bit 12
receive input data bus c bit 9, test bus bit 11
receive input data bus c bit 8, test bus bit 10
receive input data bus c bit 7, test bus bit 9
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