GC5018 Datasheet, PDF (49/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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Page Register
Contents in Hex
0x0CA0
0x0CC0
0x0CE0
0x0D00
0x0D20
0x0E00
0x0E20
0x0E40
0x0E60
0x0E80
0x0EA0
0x0EC0
0x0EE0
0x0F00
0x0F20
0x1000
0x1020
0x1040
0x1080
0x10A0
0x1100
0x1120
0x1140
0x1180
0x11A0
0x1400
0x1420
0x1440
0x1480
0x14A0
0x1500
0x1520
0x1540
0x1580
0x15A0
0x1800
0x1820
0x1840
0x1860
Address
Pin a5
0
0
0
0
0
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
Registers Addressed With 5 Bit Address Space, Pins (a4:a0)
DDC6 CFIR taps 32 through 63 coefficient lsbs (1:0)
DDC6 CFIR taps 0 through 31 coefficient msbs (17:2)
DDC6 CFIR taps 32 through 63 coefficient msbs (17:2)
DDC6 Control Registers 0x00 through 0x1F
DDC6 Control Registers 0x20 through 0x3F
0
DDC7 PFIR taps 0 through 31 coefficient lsbs (1:0)
0
DDC7 PFIR taps 32 through 63 coefficient lsbs (1:0)
0
DDC7 PFIR taps 0 through 31 coefficient msbs (17:2)
0
DDC7 PFIR taps 32 through 63 coefficient msbs (17:2)
0
DDC7 CFIR taps 0 through 31 coefficient lsbs (1:0)
0
DDC7 CFIR taps 32 through 63 coefficient lsbs (1:0)
0
DDC7 CFIR taps 0 through 31 coefficient msbs (17:2)
0
DDC7 CFIR taps 32 through 63 coefficient msbs (17:2)
0
DDC7 Control Registers 0x00 through 0x1F
0
DDC7 Control Registers 0x20 through 0x3F
0
Receive Input AGC0 Error RAM addresses 0 through 31
0
Receive Input AGC0 Error RAM addresses 32 through 63
0
Receive Input AGC0 DVGA RAM addresses 0 through 31
0
Receive Input AGC0 Gain RAM addresses 0 through 31
0
Receive Input AGC0 Gain RAM addresses 32 through 63
0
Receive Input AGC1 Error RAM addresses 0 through 31
0
Receive Input AGC1 Error RAM addresses 32 through 63
0
Receive Input AGC1 DVGA RAM addresses 0 through 31
0
Receive Input AGC1 Gain RAM addresses 0 through 31
0
Receive Input AGC1 Gain RAM addresses 32 through 63
0
Receive Input AGC2 Error RAM addresses 0 through 31
0
Receive Input AGC2 Error RAM addresses 32 through 63
0
Receive Input AGC2 DVGA RAM addresses 0 through 31
0
Receive Input AGC2 Gain RAM addresses 0 through 31
0
Receive Input AGC2 Gain RAM addresses 32 through 63
0
Receive Input AGC3 Error RAM addresses 0 through 31
0
Receive Input AGC3 Error RAM addresses 32 through 63
0
Receive Input AGC3 DVGA RAM addresses 0 through 31
0
Receive Input AGC3 Gain RAM addresses 0 through 31
0
Receive Input AGC3 Gain RAM addresses 32 through 63
0
Receive Input Control Registers 0x00 through 0x1F
0
Receive Input Control Registers 0x20 through 0x3F
0
Receive Input AGC Control Registers 0x00 through 0x1F
0
Receive Input AGC Control Registers 0x20 through 0x3F
GC5018 GENERAL CONTROL
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