GC5018 Datasheet, PDF (42/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
www.ti.com
VARIABLE
par_recv_ena
ssel_serial(2:0)
gain_mon
tristate(6:3)
PROGRAMMING
DESCRIPTION
Parallel TCI110 style interface enabled when set, serial interface enabled when cleared.
DDC channel serial interface sync source selection. All DDCs should be programmed to the same sync
source when using this parallel output interface.
When set, the parallel output data includes 8b I at I(15:8), 8b Q at Q(15:8), 14b AGC gain at I(7:0) and
Q(7:2) and 2b AGC state at Q(1:0).
3-state controls for the rx_sync_out_X and rxout_X_X pins. Pins are in 3-state when the 3-state register
bits are set.
3.2.12 DDC Checksum Generator
The checksum generator is used in conjunction with the input test signal generator to implement a self test
capability.
sync
rxclk
rxout_X_a
rxout_X_b
rxout_X_c
rxout_X_d
checksum ¹⁶
generator
results
register
checksum read−only
results updated on
each sync event
initialized on sync event to “0000 0000 0000 0010”
15
14
1312 11
10
9
3 21 0
rxout_X_a
rxout_X_b
rxout_X_c
rxout_X_d
The sync for the checksum generator is internally connected to the ddc_counter output.
VARIABLE
ddc_chk_sum(15:0)
PROGRAMMING
DESCRIPTION
Read only DDC channel checksum results
4 GC5018 GENERAL CONTROL
The GC5018 is configured over a bi-directional 16 bit parallel data microprocessor control port. The
control port permits access to the control registers which configure the chip. The control registers are
organized using a paged-access scheme using 6 address lines. Half of the 64 addresses (Address 32
through Address 63) represent global registers. The other 32 (Address 0 through Address 31) are paged
resisters. This arrangement permits accessing a large number of control registers using relatively few
address lines.
Global registers (Address 32 through Address 63) are used to read/write GC5018 parameters that are
global in nature and can benefit from single read/write operations. Examples include chip status, reset,
sync options, checksum ramp parameters, interrupt sources, interrupt masks, 3-state controls and the
page register.
42
GC5018 GENERAL CONTROL