GC5018 Datasheet, PDF (34/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
www.ti.com
PROGRAMMING
VARIABLE
DESCRIPTION
In double tap mode, data out of the last PFIR ram in the main DDC (DDC0, DDC2, DDC4 or DDC6) is
sent to the adjacent secondary DDC (DDC1, DDC3, DDC5 or DDC7) PFIR as input thus forming a
128-tap delay line. Data received from the adjacent PFIR summers is added into the Main DDC’s PFIR
sum to form the final output.
When using double tap mode, set double_tap to “10” for the main DDC, and to “01” for the secondary
DDC.
When in double tap mode, the first half of the coefficients should be loaded into the main DDC (DDC0,
DDC2, DDC4 or DDC6), the remaining coefficients are loaded into the secondary DDC (DDC1, DDC3,
DDC5 or DDC7).
In double tap mode, the main DDC must be turned on (ddc_ena=1), and the secondary DDC must be
turned off (ddc_ena=0).
The PFIR filter’s 18 bit coefficients are loaded in four 16 word memories.
Note: PFIR filter coefficients are shared between A and B channels of a DDC block when in CDMA mode.
3.2.9 DDC RMS Power Meter
18
I
18
Q
sync
36
37 _55−bit
Integrator
36
55−bit ^{RMS power}
Register
clear
transfer
8−bit
sync delay
counter
8
18−bit
interval
counter
8
18−bit
integration
counter
16
interrupt
delay
(in samples)
interval
(in 1024 sample
increments)
integration
(in 4 sample
increments)
sync
delay
interrupt
integration time
interval time
interrupt
integration time
interval time
interrupt
integration time
sync integration
event
start
integration
start
integration
start
Each DDC channel includes an RMS power meter which is used to measure the total power within the
channel pass band.
The power meter samples the I and Q data stream after the PFIR filter. Both 18 bit I and Q data are
squared, summed, and then integrated over a period determined by a programmable counter. The
integration time is a 16 bit word which is programmed into the 18 bit counter.
34
RECEIVE DIGITAL SIGNAL PROCESSING