GC5018 Datasheet, PDF (57/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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recv_
pmeter0_im
0
recv_
pmeter1_im
0
recv_
pmeter2_im
0
recv_
pmeter3_im
0
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
rxin_a_ ovr_im rxin_b_ ovr_im rxin_c_ ovr_im rxin_d_ ovr_im
0
0
0
0
pmeterX_im : When asserted, masks the interrupt for the particular DDC pmeter, X= {0,1,2,3,4,5,6,7}.
recv_pmeterX_im : When asserted, masks the interrupt for the particular receive input pmeter, X=
{0,1,2,3 }.
rxin_X_ovr_im : When asserted, masks the interrupt for the particular rxin overflow, X={a,b,c,d}.
4.4.2.9 GBL_INTERRUPT0 Register
Register name: GBL_INTERRUPT0
BIT 15
pmeter7
pmeter6
pmeter5
0
0
0
Address: 0x9
pmeter4
0
BIT 7
recv_ pmeter0
0
recv_ pmeter1
0
recv_ pmeter2
0
recv_ pmeter3
0
pmeter3
0
rxin_a_ovr
0
pmeter2
0
rxin_b_ovr
0
pmeter1
0
rcin_c_ovr
0
BIT 8
pmeter0
0
BIT 0
rxin_d_ovr
0
pmeterX : Asserted when an interrupt has been generated by this DDC pmeterX block, X={1,2,3,4,5,6,7
recv_pmeterX : Asserted when an interrupt has been generated by this receive input pmeter, X= {0,1,2,3
}.
rxin_X_ovr : Asserted when a logic high input from the rxin_X_ovr pin occurs, X={a,b,c,d}.
4.4.3 Receive Input Interface Controls
4.4.3.1 SYNC_DDC_CNTR_LSB Register
Register name: SYNC_DDC_CNTR_LSB
Address: 0x0
BIT 15
BIT 8
ddc_counter(15:8)
0
0
0
0
0
0
0
0
BIT 7
BIT 0
ddc_counter(7:0)
0
0
0
0
0
0
0
0
4.4.3.2 SYNC_DDC_CNTR_MSB
Register name: SYNC_DDC_CNTR_MSB
BIT 15
0
0
0
BIT 7
0
0
0
Address: 0x1
ddc_counter(31:24)
0
0
ddc_counter(23:16)
0
0
BIT 8
0
0
0
BIT 0
0
0
0
GC5018 GENERAL CONTROL
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