GC5018 Datasheet, PDF (15/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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VARIABLE
ssel_tst_decim(2:0)
tst_decim_delay(3:0)
tst_decim17
tst_on
tst_select(3:0)
ddc_tst_sel(5:0)
tst_rate_sel(4:0)
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
PROGRAMMING
DESCRIPTION
Selects the sync source for the testbus decimator
Sets the testbus decimator delay from sync
When set the decimation factor of the test bus output block is 17X. When cleared, the decimation factor
is 16X if the fuse is blown, 1X (no decimation) with the fuse intact.
Enables the test bus; rxin_c(15:0) and rxin_d(15:0) are changed from inputs to outputs, dvga_c(5:0) and
dvga_d(5) are used as part of the test bus.
Selects the source block for the testbus output; DDC0-7 or Receive Interface.
Selects the signal to be output from the DDC block
Sets the testbus output clock tst_clk period to (tst_rate_sel + 1) rxclk cycles.
3.2 DDC Organization
18
18
4 to 2 (complex) or
18
4 to 1 (real) switch
CDMA DDC A
18
or 1 UMTS DDC
Output
Interface
4 to 2 (complex) or
4 to 1 (real) switch
CDMA DDC B
DDC0
DDC1
DDC2
DDC3
DDC4
DDC5
DDC6
DDC7
The GC5018 provides downconversion for up to 8 UMTS receive channels, 16 CDMA2000 receive
channels or 16 TD-SCDMA receive channels. Downconversion channels are organized into 8 DDC blocks.
Each individual DDC block provides 2 CDMA2000 or 2 TD-SCDMA DDC channels, A and B, or 1 UMTS
channel.
Both CDMA DDC channels in a DDC block can be independently tuned, though they would likely be used
as diversity pairs and tuned to the same frequency. Filter coefficients are shared between the two CDMA
DDC channels within a block.
Two adjacent DDC blocks (for example, DDC0 and DDC1) can be strapped together to form a single
UMTS DDC channel with double-length final pulse shaping filtering. The GC5018 can therefore provide 4
UMTS DDC channels with double-length final PFIR filtering as shown in the following diagram.
RECEIVE DIGITAL SIGNAL PROCESSING
15