GC5018 Datasheet, PDF (58/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
www.ti.com
ddc_counter(32:0) : 32 bit interval timer common to all DDC sync inputs. This timer may be programmed
to any interval count, and each DDC synchronization input can select this counter as a
source. The value programmed into the counter is: (desired number –1). The counter
increments on each RX clock rising edge.
4.4.3.3 SSEL_DDC_CNTR Register
Register name: SSEL_DDC_CNTR
BIT 15
rxinab_mux
rxincd_mux
0
0
unused
0
BIT 7
0
0
0
Address: 0x2
unused
0
unused
0
ddc_counter_width(7:0)
0
0
BIT 8
ssel_ddc_counter(2:0)
0
0
0
BIT 0
0
0
0
rxinab_mux : When asserted, the rxin_a and rxin_b inputs are internally driven by the rxin_c and rxin_d
ports, respectively (Factory test use only).
rxincd_mux : When asserted, the rxin_c and rxin_d inputs are internally driven by the rxin_a and rxin_b
ports, respectively (Factory test use only).
ssel_ddc_counter(2:0) : Selects the sync source for the DDC sync counter.
ddc_counter_width(7:0) : Sets the width of the counter generated sync pulse in RX clock cycles, from 1
to 256.
Sync sources are contained in this and many of the following registers. For all sync source selections:
ssel_ddc_XXXXX(2:0)
000
001
010
011
100
101
110
111
Selected Sync Source
rxsyncA
rxsyncB
rxsyncC
rxsyncD
DDC sync counter
one shot (register write triggered)
always 0
always 1
4.4.3.4 SSEL_RX_0 Register
Register name: SSEL_RX_0
BIT 15
unused
0
0
Address: 0x3
ssel_adc_fifo(2:0)
0
0
BIT 7
unused
0
ssel_rxsync_out(2:0)
0
0
0
unused
0
unused
0
BIT 8
ssel_tst_decim(2:0)
0
0
0
BIT 0
ssel_ddc(2:0)
0
0
0
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GC5018 GENERAL CONTROL