GC5018 Datasheet, PDF (20/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
VARIABLE
ssel_nco(2:0)
ssel_dither(2:0)
ssel_freq(2:0)
ssel_phase(2:0)
SYNC PROGRAMMING
DESCRIPTION
Sync source for NCO accumulator reset
Sync source for NCO dither reset
Sync source for NCO frequency register loading
Sync source for NCO phase register loading
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3.2.4 DDC Filtering and Decimation
The purpose of the receive filter chain is to isolate the signal of interest (and reject all other others) that
has been previously translated to baseband via the mixer and NCO. The overall decimation through the
chain needs to be considered. The goal, generally, is to output the isolated signal at a rate that is twice
(2X) the signal’s chip rate. For UMTS this would be 7.68 MSPS and for CDMA the output rate should be
2.4576 MSPS. TD-SCDMA systems require the output rate be the chip rate of 1.28 MSPS. The output
interface is programmed to decimate by 2 for the TD-SCDMA case.
Receive filtering and decimation is performed in several stages:
• Zero padding to interpolate the input sample rate (if needed) up to the rxclk rate
• High rate decimation (4 to 32) using a six stage cascade-integrate-comb filter (CIC)
• Decimate by two compensation filtering using the programmable compensating FIR filter (CFIR)
• Pulse-shape filtering via the programmable FIR filter (PFIR) with no decimation
• Output interface, serial or parallel format, with no decimation or decimate by 2
From
Mixer
Delay
Adjust
Zero Pad
Interp by {1,2,4,8}
Six Stage
CIC Filter
Dec by {4 −32}
CFIR Filter
Dec by 2
PFIR Filter
no decimation
Output Interface
Dec by {1,2}
The table below contains some examples of decimation and sample rates at the output of each block for
UMTS, CDMA and TD-SCDMA standards at various supported input samples. For each example, the
differential ADC clocks are provided to the GC5018 at the input sample rate and the rxclk is provided at
the zero pad output rate.
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RECEIVE DIGITAL SIGNAL PROCESSING