GC5018 Datasheet, PDF (39/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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VARIABLE
ssel_agc_freeze(2:0)
ssel_gain(2:0)
ssel_ddc_agc(2:0)
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
PROGRAMMING
DESCRIPTION
Note: Bit 0 of Status, when set, indicates the data is saturated. Bit 1 of Status, when set, indicates the data is
zero.
Sync selection for freeze mode, 1 of 8 sources. This source is ORed with the freeze register bit
Sync selection for the double buffered agc_gaina and agc_gainb register.
Sync selection used to initialize the AGC, primarily for test purposes.
3.2.11 DDC Output Interface
The baseband I/Q sample interface can be configured as serial or parallel formatted data. The serial
interface closely matches the GC5316 style interface. The parallel interface is provided to interface directly
to the TMS320TCI110 when delayed antenna streams used to implement channel estimation buffering
and/or transport format combination indicator (TFCI) buffering are not required.
3.2.11.1 Serial Output Interface
sync
clkdiv ⁴
frame
strobe
2
delay
DDC Block
1 UMTS mode channel or
2 CDMA mode channels
rxout_X_a
rxout_X_b
rxout_X_c
rxout_X_d
CDMA
I ch A
I ch B
Q ch A
Q ch B
Serial Outputs
UMTS
I msb
I msb−1
Q msb
Q msb−1
double length
PFIR UMTS
I msb
I msb−1
I msb−2
I msb−3
rx_sync_out_X
four outputs from
adjacent DDC block
Q msb
Q msb−1
Q msb−2
Q msb−3
Each DDC block can be assigned four serial output data pins. These pins are used to transfer
downconverted I/Q baseband data out of the GC5018 for subsequent processing. The usage of these pins
changes depending on how the DDC block is configured.
When the block is configured for two CDMA channels, a pair of serial data pins provides separate I and Q
data output for the two DDC channels. Word size is selectable from 4 to 25 bits with the most significant
bit first.
When the DDC block is configured for a single UMTS channel, even and odd I and Q data drive the four
serial pins separately, most significant bit first.
Four serial pins each for I and Q data can be optionally employed (instead of two for I and two for Q) at
half the output rate. This would most likely be used when two DDC channels (2k and 2k + 1, k= 0 to 5) are
combined to support double-length PFIR filtering (a channel is sacrificed). Formatting for I data is then:
Imsb, Imsb-1, Imsb-2, Imsb-3. Q data formatting is: Qmsb, Qmsb-1, Qmsb-2, Qmsb-3.
The frame strobe signal provided on the rx_sync_out_X pins can be programmed to arrive from 0 to 3 bit
clocks early via a 2 bit control parameter. The frame interval can be programmed from 1 to 63 bits. A
programmable 4-bit clock divider circuit is used to specify the serial bit rate. The clock divider circuit is
synchronized using a sync block discussed later in this document.
RECEIVE DIGITAL SIGNAL PROCESSING
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