GC5018 Datasheet, PDF (11/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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VARIABLE
ragc_accum_X(31:0)
tristate(10:7)
ragc_mpu_ram_read
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
PROGRAMMING
DESCRIPTION
32-bit read only register holding the current contents of the loop accumulator.
3-state controls for the dvga_d/c/b/a output pins; pins are in tristate when the 3-state bits are set.
What set, the receive AGC map rams are readable via the MPU control interface. The GC5018 signal
path is not operational when this bit is set, it is intended for debug purposes only.
3.1.4 Test and Noise Signal Generator
The test and noise generator can generate test signals to replace the rxin_a/b/c/d inputs as a tool for
debug, evaluation and self test. Checksum generators included in the individual DDC channels at the
outputs can be used in conjunction with the noise generator and the internal sync timer block to create the
built in self test function.
The test and noise signal source included in this block is a 23-bit linear feedback shift register (LFSR) with
a fixed polynomial and fixed initialization state. A sync input is required to initialize the LFSR, and the sync
source is connected to the ddc_counter output signal.
sync
adcclk_X
LFSR
lfsr (22:0)
initialized on sync event − each of the four generators has a different seed
22
5
0
Receive Input Port
rxin_a
rxin_b
rxin_c
rxin_d
LFSR Seed Value, MSB to LSB
100 0000 0000 0000 0001 0000 (0x400010)
010 0110 1110 0110 1100 1110 (0x26E6CE)
110 1110 1010 0010 1001 1000 (0x6EA298)
000 1011 0001 1110 1011 0111 (0x0B1EB7)
RECEIVE DIGITAL SIGNAL PROCESSING
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