GC5018 Datasheet, PDF (4/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
3.1 Receive Input Interface
dvga_a
rxin _a 16
test & noise ¹⁶
signal
generator
to testbus
6
FIFO ¹⁶
dual real or
single complex
Power Meter
rxin _b
16
test & noise ¹⁶
signal
generator
FIFO ¹⁶
dvga_b
6
dvga_c
rxin _c 16
test & noise ¹⁶
signal
generator
test bus select
and decimation
6
FIFO ¹⁶
testbus
sources
dual real or
single complex
Power Meter
rxin _d
16
test & noise ¹⁶
signal
generator
FIFO ¹⁶
dvga_d
6
dual real or
single complex
AGC
dual real or
single complex
AGC
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18
1 to 64
sample
delay
line
delay_a ₁₈
1 to 64
sample
delay
line
delay_b
18
1 to 64
sample
delay
line
delay_c ₁₈
1 to 64
sample
delay
line
rx_distribution
bus to DDC
channels
delay_d
The GC5018’s receive input data interface accepts data from two sources:
• Signal data presented at the four 16-bit digital data input ports.
• A LFSR test signal generator allows the GC5018 to be tested using a known repetitive data sequence.
Signal data can be provided in binary or 2’s complement form. The location of the ADC’s MSB can be
programmed to allow for additional AGC headroom if desired. For example, a 14-bit ADC may be
connected with the MSBs aligned, or shifted down to allow the AGC additional gain range before clipping
the signal.
Signal data can be accepted at rates up to rxclk in UMTS mode for either 8 normal channels or 4 double
length final pulse shaping filter channels. In CDMA mode the maximum input rate is rxclk for real inputs, or
rxclk/2 for complex inputs. For maximum filter performance, higher clock rates generally allow longer
filters.
Complex signal data is input with I data driving one input port and Q data driving another. This means that
there are only two signal data ports available when using complex input mode. The mapping of I and Q
data onto the four input ports is programmable.
Signal input data is clocked into 8-stage FIFOs using a matching external clock signal adcclk_a/b/c/d.
Signal data is clocked out of the FIFO from a gated rxclk (the GC5018 receive section clock). The FIFO
allows arbitrary phase relationship between adcclk_a/b/c/d and rxclk. The frequency relationship is
mandated by the programmed configuration.
The test and noise generator can supply test sequences or add noise to the input signal data. The test
sequences, when combined with the checksum generators, are useful for initial board debug or power-on
self-test.
For applications that require receiver desensitization, the noise generator can add noise to input data
streams.
Many internal chip signals can be routed to the testbus for evaluation and debug purposes. When the
testbus is enabled, the rxin_c and rxin_d ports are driven as digital outputs.
4
RECEIVE DIGITAL SIGNAL PROCESSING