GC5018 Datasheet, PDF (41/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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3.2.11.2 Parallel Output Interface
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
Output
format
rx_sync_out_6
rxclk _out
rxout_7_d
rxout_7_c
rxout_7_b
par_sync_out
rxclk _out
I(15)
I(14)
I(13)
rxout_4_b
rxout_4_a
rxout_3_d
rxout_3_c
rxout_3_b
I(1)
I(0)
Q(15)
Q(14)
Q(13)
Parallel I/Q
rxout_0_b
rxout_0_a
Q(1)
Q(0)
When a parallel I/Q interface is required, a 32 bit time division multiplexed output mode can be selected
using the rxout_X_X pins. This interface is provided for direct connection to the TMS320TCI110 Receive
Chip Rate ASSP when delayed antenna streams are not required. The output sample rate, rxclk_out clock
polarity, par_sync_out position and number of channels to be output are all programmable.
rxclk_out
par_sync_out
Parallel I/Q
IQ DDC0
IQ DDC1
IQ DDC2
IQ DDC3
IQ DDC4
IQ DDC5
IQ DDC6
IQ DDC7
The DDC channel serial interface synchronization source selections should all be programmed to the
same value when using this parallel output interface (each DDC channel ssel_serial(2:0) in the SYNC_0
register should be programmed to the same rxsync_A/B/C/D value).
Decimation by 2 in the output interface can be achieved by setting the frame strobe interval and clock
divider to 1/2 the PFIR output rate. The parallel interface samples the PFIR outputs each time the transfer
interval defined by these two settings has completed.
VARIABLE
par_recv_fsinvl(6:0)
par_recv_clkdiv(6:0)
par_recv_chan(3:0)
par_recv_sync_del(6:0)
par_recv_syncout_del(3:0)
par_recv_rxclk_pol
par_recv_sync_pol
PROGRAMMING
DESCRIPTION
rx_sync_out (frame strobe) sync interval. 0 is 1 rxclk cycle and 127 is 128 rxclk cycles.
rxclk_out cycles per IQ channel sample; 1 is full rate, 2 is rxclk/2, etc.
Number channels to be output. 0 is 1 channel, and 15 is 16 channels.
Delays the DDC0 pser sync source to establish the timing of IQ DDC0. Increasing the value delays the
par_sync_out location.
Delays the rx_sync_out position with respect to IQ DDC0. Setting to 0 moves the rx_sync_out pulse one
rxclk_out cycle before the IQ DDC0 word, setting to 1 places it as shown above, lined up with IQ DDC0,
etc.
rxclk_out polarity. Outputs data on falling edges when cleared, rising edges when set.
Parallel interface par_sync_out polarity. 0 is active low, 1 for active high
RECEIVE DIGITAL SIGNAL PROCESSING
41