GC5018 Datasheet, PDF (47/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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VARIABLE
pmeterX_im(7:0)
recv_pmeterX_im(3:0)
rxin_X_ovr_im
pmeterX(7:0)
recv_pmeterX(3:0)
rxin_X_ovr
intr_clr
3-state(0)
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
PROGRAMMING
DESCRIPTION
Channel pmeter interrupt mask bits. Interrupt source is masked when set.
Receive input power meter interrupt masks.
ADC overflow input pin interrupt masks.
Channel pmeter interrupt status.
Receive input power meter interrupt status.
ADC overflow input pin interrupt status.
When asserted, holds all interrupt status bits cleared. The interrupt pin will be inactive (always low) when this
bit is set. Intended for lab/debug use only
When set, the interrupt and rx_sync_out pins are 3-stated.
4.4 GC5018 Programming
The GC5018 includes over 3000 internal configuration registers and therefore implements a paged
addressing scheme. The register map includes a global control variables register address space that is
accessed directly when the a5 signal is high. This global control variables address space includes the
page register. All other registers are addressed using a combination of an address comprised of the
internal page register contents and the 6-bit external address; a5, a4, a3, a2, a1 and a0.
The page register is accessed when the 6-bit address a5:a0 is 0x21 (or binary “100001”).
Page Register
Contents in Hex
don’t care
Address
Pin a5
1
Registers Addressed With 5 Bit Address Space, Pins (a4:a0)
Global Control Variables 0x00 through 0x1F
0x0000
0x0020
0x0040
0x0060
0x0080
0x00A0
0x00C0
0x00E0
0x0100
0x0120
0
DDC0 PFIR taps 0 through 31 coefficient lsbs (1:0)
0
DDC0 PFIR taps 32 through 63 coefficient lsbs (1:0)
0
DDC0 PFIR taps 0 through 31 coefficient msbs (17:2)
0
DDC0 PFIR taps 32 through 63 coefficient msbs (17:2)
0
DDC0 CFIR taps 0 through 31 coefficient lsbs (1:0)
0
DDC0 CFIR taps 32 through 63 coefficient lsbs (1:0)
0
DDC0 CFIR taps 0 through 31 coefficient msbs (17:2)
0
DDC0 CFIR taps 32 through 63 coefficient msbs (17:2)
0
DDC0 Control Registers 0x00 through 0x1F
0
DDC0 Control Registers 0x20 through 0x3F
0x0200
0x0220
0x0240
0x0260
0x0280
0x02A0
0x02C0
0x02E0
0x0300
0x0320
0x0400
0x0420
0
DDC1 PFIR taps 0 through 31 coefficient lsbs (1:0)
0
DDC1 PFIR taps 32 through 63 coefficient lsbs (1:0)
0
DDC1 PFIR taps 0 through 31 coefficient msbs (17:2)
0
DDC1 PFIR taps 32 through 63 coefficient msbs (17:2)
0
DDC1 CFIR taps 0 through 31 coefficient lsbs (1:0)
0
DDC1 CFIR taps 32 through 63 coefficient lsbs (1:0)
0
DDC1 CFIR taps 0 through 31 coefficient msbs (17:2)
0
DDC1 CFIR taps 32 through 63 coefficient msbs (17:2)
0
DDC1 Control Registers 0x00 through 0x1F
0
DDC1 Control Registers 0x20 through 0x3F
0
DDC2 PFIR taps 0 through 31 coefficient lsbs (1:0)
0
DDC2 PFIR taps 32 through 63 coefficient lsbs (1:0)
GC5018 GENERAL CONTROL
47