GC5018 Datasheet, PDF (14/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
www.ti.com
3.1.5 Sample Delay Lines
The four sample delay line blocks each consist of a 64 register memory and a state machine. The state
machine uses a counter to control the write (input) pointer, and the programmed read offset register data
to create the read (output) pointer. Programming larger read offset register values increases the effective
delay at a resolution equal to the sample rate.
The read offset registers, delay_line_X, are double buffered. Writes to these registers may occur anytime,
but the actual values used by the circuit will not be updated until a delay line sync event occurs.
VARIABLE
delay_line_X(5:0)
ssel_delay_line_X(2:0)
PROGRAMMING
DESCRIPTION
Read offset into the 64 element memory for each delay line. X= {0,1,2,3}.
Selects the sync source used to update the double buffered delay line register.
3.1.6 Test Bus
When the test bus is enabled, the rxin_c(15:0) and rxin_d(15:0) ports become outputs, and the dvga_c
and dvga_d pins are combined with these pins to allow 36 bit wide signals from the DDC channels and the
receive input interface to be multiplexed to this test output port. Many of these sources can be decimated
to reduce the output sample rates.
DDC0
zeros
pfir output
cfir output
tadjchannel A
tadjchannel B
ncosin
ncocos
cicoutput
mixer i*cos& i*sin
mixer qc*os& q*sin
ddcmux channel A
ddcmuxchannel B
DDC1
MUX
ddc_tst_sel(5:0)
DDC2
DDC3
DDC4
DDC5
DDC6
DDC7
Receive Interface
rxin_a& rxin_b FIFO outputs
MUX
tst_select(3:0)
DECIMATE (35:20)
tst_decim17 (19:18)
tst_decim_delay(17:2)
(1:0)
tst_clk
tst_aflag
tst_sync
rxin_d(15:0)
dvga_c(3:2)
rxin_c(15:0)
dvga_c(5:4)
dvga_c(1)
dvga_d(5)
dvga_c(0)
sync
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RECEIVE DIGITAL SIGNAL PROCESSING