GC5018 Datasheet, PDF (73/115 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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Register name: RAGC0_CONFIG0
BIT 15
0
0
0
BIT 7
hp_corner_0(2:0)
0
0
0
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169 – MAY 2005
Address: 0x6
ragc_sync_delay_0(7:0)
0
0
0
0
acc_shift_0(4:0)
0
0
0
0
BIT 8
0
BIT 0
0
ragc_sync_delay_0(7:0) : The input sync to the receive AGC block is delayed by this number of samples.
hp_corner_0(2:0) : Sets the corner frequency of the high pass filter. Larger values result in higher corner
frequencies
acc_shift_0(4:0) : Selects the integrated power measurements result bits to be used as the error lookup
table address. A larger number means fewer samples will have to be integrated to achieve
the same result.
4.4.4.8 RAGC0_CONFIG1 Register
Register name: RAGC0_CONFIG1
BIT 15
0
BIT 7
0
0
err_shift_0(2:0)
0
acc_offset_0(5:0)
0
0
0
0
Address: 0x7
0
0
delay_adj_0(4:0)
0
0
BIT 8
err_shift_0(4:3)
0
0
BIT 0
0
0
acc_offset_0(5:0) : Constant subtracted from the integrated power measurement result before the error
lookup table.
err_shift_0(4:0) : Adjusts the loop gain by controlling the amount of shifting applied to the error lookup
table output. Larger values result in higher gain.
delay_adj_0(4:0) : Sets the delay difference, in samples, between the DVGA outputs and the value
applied to the sample multiplier.
4.4.4.9 RAGC0_SD_THRESH Register
Register name: RAGC0_SD_THRESH
BIT 15
0
0
0
BIT 7
0
0
0
Address: 0x8
sd_thresh_0(15:8)
0
0
0
sd_thresh_0(7:0)
0
0
0
BIT 8
0
0
BIT 0
0
0
sd_thresh_0(15:0) : This is the threshold used by the Signal Detect block to determine if there is signal
on the inputs. The comparison is done to the output of the squarer block, which is a 32 bit
word. Because of this, these bits are aligned with bits 24 down to 8 of the 32 bit squared
value.
GC5018 GENERAL CONTROL
73