SI5338 Datasheet, PDF (9/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
Table 6. Input and Output Clock Characteristics (Continued)
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Output Clocks (Single-Ended)
Frequency
f_OUT
CMOS
SSTL, HSTL
0.16
—
0.16
—
200
MHz
350
MHz
CMOS 20%–80%
Rise/Fall Time
CMOS 20%–80%
Rise/Fall Time
CMOS Output Resis-
tance
SSTL Output
Resistance
HSTL Output
Resistance
CMOS Output Voltage⁵
SSTL Output Voltage
HSTL Output Voltage
Duty Cycle²
t_R/t_F
2 pF load
—
t_R/t_F
15 pF load
—
—
—
—
V_OH
4 mA load
VDDO – 0.3
V_OL
4 mA load
V_OH
SSTL-3 VDDOx = 2.97 ^{0.45xVDDO+0.41}
V_OL
to 3.63 V
—
V_OH
SSTL-2 VDDOx = 2.25 ^{0.5xVDDO+0.41}
V_OL
to 2.75 V
—
V_OH
SSTL-18 VDDOx = 1.71 ^{0.5xVDDO+0.34}
V_OL
to 1.98 V
—
V_OH
0.5xVDDO+0.3
VDDO = 1.4 to 1.6 V
V_OL
—
DC
45
0.45
—
50
50
50
—
—
—
—
—
—
—
—
—
—
—
0.85
ns
1.7
ns
—

—

—

V
0.3
V
—
V
0.45xVDDO–0.41 V
—
V
0.5xVDDO–0.41 V
V
0.5xVDDO–0.34 V
—
V
0.5xVDDO –0.3 V
55
%
Notes:
1. For best jitter performance, keep the input slew rate on pins 1,2,5,6 faster than 0.3 V/ns
2. Not in PLL bypass mode.
3. For best jitter performance, keep the input single ended slew rate on pins 3 or 4 faster than 1 V/ns
4. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6.
5. Includes effect of internal series 22  resistor.
Rev. 0.6
9