SI5338 Datasheet, PDF (162/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
Pin # Pin Name
5,6
IN5/IN6
7
VDD
8
INTR
9
CLK3B
10
CLK3A
11
VDDO3
12
SCL
13
CLK2B
14
CLK2A
Table 17. Si5338 Pin Descriptions (Continued)
I/O
I
VDD
O
O
O
VDD
I
O
O
Signal Type
Description
Multi
FDBK/FDBKB.
These pins can be used as a differential feedback input in zero
delay mode or as a secondary clock input. See section 3.2,
Figure 3, for termination details. See "3.9.5. Zero-Delay Mode" on
page 24 for zero delay mode set-up. Inputs to these pins must be
ac-coupled.
When not in use, leave IN5 unconnected and IN6 connected to
GND.
Supply
Core Supply Voltage.
This is the core supply voltage, which can operate from a 1.8, 2.5,
or 3.3 V supply. A 0.1 µF bypass capacitor should be located very
close to this pin.
Open Drain
Interrupt.
A typical pullup resistor of 1–4 k is used on this pin. This pin can
be pulled up to a supply voltage as high as 3.6 V regardless of the
other supply voltages on pins 7, 11, 15, 16, 20, and 24. The inter-
rupt condition allows the pull up resistor to pull the output up to the
supply voltage.
Multi
Output Clock B for Channel 3.
May be a single-ended output or half of a differential output with
CLK3A being the other differential half. If unused, leave this pin
floating.
Multi
Output Clock A for Channel 3.
May be a single-ended output or half of a differential output with
CLK3B being the other differential half. If unused, leave this pin
floating.
Supply
LVCMOS
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK3A,B. A 0.1 µF
capacitor must be located very close to this pin. If CLK3 is not
used, this pin must be tied to VDD (pin 7, 24).
I²C Serial Clock Input.
This is the serial clock input for the I²C bus. A pullup resistor at this
pin is required. Typical values would be 1–4 k. See the I²C bus
spec for more information. This pin is 3.3 V tolerant regardless of
the other supply voltages on pins 7, 11, 15, 16, 20, 24.
Multi
Output Clock B for Channel 2.
May be a single-ended output or half of a differential output with
CLK2A being the other differential half. If unused, leave this pin
floating.
Multi
Output Clock A for Channel 2.
May be a single-ended output or half of a differential output with
CLK2B being the other differential half. If unused, leave this pin
floating.
162
Rev. 0.6