SI5338 Datasheet, PDF (103/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
Register 114.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name CLK1_DISST[1:0]
MS1_PHSTEP[13:8]
Type
R/W
R/W
Reset value = xxxx xxxx
Bit
Name
Function
MultiSynth1 Output Driver State When Disabled.
00: High impedance
7:6
CLK1_DISST[1:0]
01: Logic low
10: Logic high
11: Always on even if disabled
MultiSynth1 Phase Step Size.
The phase step size is MS1_PHSTEP[13:0]*Tvco/128 where Tvco is
5:0
MS1_PHSTEP[13:8]
the period of the VCO. Either the phase inc/dec pins (if available) or
register 63[1:0] will control the stepping of phase. A phase increment
will delay the clock edge.
Register 115.
Bit
D7
D6
Name
Type
Reset value = xxxx xxxx
Bit
Name
7:0
MS2_PHOFF[7:0]
D5
D4
D3
D2
D1
D0
MS2_PHOFF[7:0]
R/W
Function
MultiSynth2 Initial Phase Offset.
MultiSynth2_PHOFF[14:0] is a 2s complement number. The initial phase
offset is MultiSynth2_PHOFF[14:0] x Tvco/128 where Tvco is the period
of the VCO.
Rev. 0.6
103