SI5338 Datasheet, PDF (17/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
3.2. Input Stage
The input stage supports four inputs. Two are used as
the clock inputs to the synthesis stage, and the other
two are used as feedback inputs for zero delay or
external feedback mode. In cases where external
feedback is not required, all four inputs are available to
the synthesis stage. The reference selector selects one
of the inputs as the reference to the synthesis stage.
The input configuration is selectable through the I^C
interface. The input MUXes are set automatically in
ClockBuilder Desktop (see “3.1.1. ClockBuilder™
Desktop Software”). For information on setting the input
MUXs manually, see “AN411: Configuring the Si5338”.
Osc
noclk
IN1
P1DIV_IN
IN2
÷P1
IN3
IN3 and IN4 accept single-ended signals from 5 MHz to
200 MHz. The single-ended inputs are internally ac-
coupled; so, they can accept a wide variety of signals
without requiring a specific dc level. The input signal
only needs to meet a minimum voltage swing and must
not exceed a maximum VIH or a minimum VIL. Refer to
Table 6 for signal voltage limits. A typical single-ended
connection is shown in Figure 3. For additional
termination options, refer to “AN408: Termination
Options for Any-Frequency, Any-Output Clock
Generators and Clock Buffers—Si5338, Si5334,
Si5330”.
For free-run operation, the internal oscillator can
operate from a low-frequency fundamental mode crystal
(XTAL) with a resonant frequency between 8 and
30 MHz. A crystal can easily be connected to pins IN1
and IN2 without external components as shown in
Figure 4. See Tables 8–11 for crystal specifications that
are guaranteed to work with the Si5338.
IN1
P2DIV_IN
IN4
IN5
÷P2
XTAL
Osc
To synthesis stage
or output selectors
IN6
noclk
IN2
Figure 2. Input Stage
IN1/IN2 and IN5/IN6 are differential inputs capable of
accepting clock rates from 5 to 710 MHz. The
differential inputs are capable of interfacing to multiple
signals, such as LVPECL, LVDS, HSCL, HCSL, and
CML. Differential signals must be ac-coupled as shown
in Figure 3. A termination resistor of 100  placed close
to the input pins is also required. Refer to Table 6 for
signal voltage limits.
0.1 uF
50
100
50
IN1 / IN5
IN2 / IN6
0.1 uF
Rs
50
IN3 / IN4
Figure 3. Interfacing Differential and Single-
Ended Signals to the Si5338
Figure 4. Connecting an XTAL to the Si5338
Refer to “AN360: Crystal Selection Guide for Si533x/5x
Devices” for information on the crystal selection.
3.2.1. Loss-of-Signal (LOS) Alarm Detectors
There are two LOS detectors: LOS_CLKIN and
LOS_FDBK. These detectors are tied to the outputs of
the P1 and P2 frequency dividers, which are always
enabled. See "3.6. Status Indicators" on page 22 for
details on the alarm indicators. These alarms are used
during programming to ensure that a valid input clock is
detected. The input MUXs are set automatically in
ClockBuilder Desktop (see AN411 to set manually).
3.3. Synthesis Stages
Next-generation timing applications require a wide
range of frequencies that are often non-integer related.
Traditional clock architectures address this by using
multiple single PLL ICs, often at the expense of BOM
complexity and power. The Si5338 uses patented
MultiSynth technology to dramatically simplify timing
architectures by integrating the frequency synthesis
capability of four Phase-Locked Loops (PLLs) in a
single device, greatly reducing size and power
requirements versus traditional solutions.
Rev. 0.6
17