SI5338 Datasheet, PDF (104/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
Register 116.
Bit
D7
D6
Name
Type
R/W
Reset value = xxxx xxxx
Bit
Name
7
Reserved
6:0
MS2_PHOFF[14:8]
D5
D4
D3
D2
D1
D0
MS2_PHOFF[14:8]
R/W
Function
Reserved.
Must write 1b to this bit.
MultiSynth2 Initial Phase Offset.
MultiSynth2_PHOFF[14:0] is a 2s complement number. The initial
phase offset is MultiSynth2_PHOFF[14:0] x Tvco/128 where Tvco is
the period of the VCO.
Register 117.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
MS2_PHSTEP[7:0]
Type
R/W
Reset value = xxxx xxxx
Bit
Name
Function
MultiSynth2 Phase Step Size.
The phase step size is MultiSynth2_PHSTEP[13:0] x Tvco/128 where
7:0
MS2_PHSTEP[7:0]
Tvco is the period of the VCO. Either the phase inc/dec pins (if avail-
able) or register 74[1:0] will control the stepping of phase. A phase
increment will delay the clock edge.
104
Rev. 0.6