SI5338 Datasheet, PDF (13/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
Table 12. Jitter Specifications^1,2 (Continued)
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Deterministic Jitter
Output MultiSynth
operated in fractional
—
3
15 ps pk-pk
D_J
mode⁵
Output MultiSynth
operated in integer
—
2
10 ps pk-pk
mode⁵
Total Jitter
(12 kHz–20 MHz)
Output MultiSynth
operated in fractional
—
T_J = D_J+14xR_J ^mode5
(See Note ⁷) _{Output MultiSynth}
operated in integer
—
mode⁵
13
36 ps pk-pk
12
20 ps pk-pk
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL output format with a low noise differential input clock and are
made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. For best jitter performance, keep the single ended clock input slew rates at Pins 3 and 4 more than 1.0 V/ns and the
differential clock input slew rates more than 0.3 V/ns.
3. D_J for PCI and GBE is < 5 ps pp
4. Output MultiSynth in Integer mode.
5. Input frequency to the Phase Detector between 25 and 40 MHz and any output frequency > 5 MHz.
6. Measured in accordance with JEDEC standard 65.
7. Rj is multiplied by 14; estimate the pp jitter from Rj over 2¹² rising edges.
Table 13. Typical Phase Noise Performance
Offset Frequency
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
25MHz XTAL
to 156.25 MHz
–90
–120
–126
–132
–132
–145
27 MHz Ref In
to 148.3517 MHz
–87
–117
–123
–130
–132
–145
19.44 MHz Ref In
to 155.52 MHz
–110
–116
–123
–128
–128
–145
Units
dBc/Hz
Rev. 0.6
13