SI5338 Datasheet, PDF (6/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
Table 5. Performance Characteristics
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ
PLL Acquisition Time
t_ACQ
—
—
PLL Lock Range
f_LOCK
5000 —
PLL Loop Bandwidth
MultiSynth Frequency
Synthesis Resolution
f_BW
—
1.6
f_RES
Output frequency < Fvco/8
0
0
CLKIN Loss of Signal Detect
t_LOS
Time
—
2.6
CLKIN Loss of Signal Release
Time
t_LOSRLS
0.01 0.2
PLL Loss of Lock Detect Time
t_LOL
—
5
Max
25
—
—
1
5
1
10
Unit
ms
ppm
MHz
ppb
µs
µs
ms
POR to Output Clock Valid
(Pre-programmed Devices)
t_RDY
—
—
2
ms
Input-to-Output Propagation
Delay
Output-Output Skew
POR to I²C Ready
t_PROP
t_DSKEW
Buffer Mode
(PLL Bypass)
Rn divider = 1¹
—
2.5
—
ns
—
—
100
ps
—
—
15
ms
Programmable Initial
Phase Offset
P_OFFSET
–45
—
+45
ns
Phase Increment/Decrement
Accuracy
P_STEP
—
—
20
ps
Phase Increment/Decrement
Range
P_RANGE
–45
—
+45
ns
Frequency range for phase
increment/decrement
f_PRANGE
—
—
350²
MHz
Phase Increment/Decrement
P_UPDATE
Pin control^2,3
667
—
—
ns
Update Time
MultiSynth output >18 MHz
Notes:
1. Outputs at integer-related frequencies and using the same driver format. See "3.9.3. Initial Phase Offset" on page 24.
2. The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept
between 5 MHz and Fvco/8.
3. Update rate via I²C is also limited by the time it takes to perform a write operation.
4. Default value is 0.5% down spread.
5. Default value is ~31.5 kHz.
6
Rev. 0.6