SI5338 Datasheet, PDF (137/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
Register 218.
Bit
D7
D6
Name
Type
Reset value = 0000 0000
Bit
Name
7:5
Reserved
4
PLL_LOL
3
LOS_FDBK
2
LOS_CLKIN
1
Reserved
0
SYS_CAL
D5
D4
D3
D2
D1
D0
PLL_LOL LOS_FDBK LOS_CLKIN
SYS_CAL
R
R
R
R
Function
Reserved
PLL Loss of Lock (LOL).
Asserts when the two PFD inputs have a frequency difference > 1000 ppm.
This bit is held high during a POR_reset until the PLL has locked. This bit will not
chatter while the PLL is locking. PLL_LOL does not assert when the input from
IN1,IN2 or IN3 is lost. When PLL_LOL asserts, the part will automatically try to
re-acquire to the input clock. See Register 241[7].
Loss of Signal on Feedback Clock from IN5,6 or IN4.
Loss of Signal on Input Clock from IN1,2 or IN3.
Reserved
Device Calibration in Process.
Rev. 0.6
137