SI5338 Datasheet, PDF (73/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
Register 52.
Bit D7
Name
Type
D6
D5
MS0_FIDCT[1:0]
R/W
Reset value = xxxx xxxx
Bit
Name
7
Reserved
6:5
MS0_FIDCT[1:0]
4
MS0_FIDDIS
3:2
MS0_SSMODE[1:0]
1:0
MS0_PHIDCT[1:0]
D4
MS0_FIDDIS
R/W
D3
D2
MS0_SSMODE[1:0]
R/W
D1
D0
MS0_PHIDCT[1:0]
R/W
Function
Reserved.
MultiSynth0 Frequency Increment/Decrement Control.
Bit 4 (disable) must be 0 before writing an increment or decrement
to these bits. Only MS0 can have pin control of Frequency Incre-
ment/Decrement.
0: No frequency inc/dec on MS0
1: Enable pin control of frequency inc/dec
2: Frequency increment on MS0, self-clearing
3: Frequency decrement on MS0, self-clearing
MultiSynth0 Frequency Increment/Decrement Disable (see also
Register 242[1]).
0: Frequency inc/dec enabled on MS0
1: Frequency inc/dec disabled on MS0
MultiSynth0 Spread Spectrum Mode Select.
0: No SSC on MS0
1: Center spread on MS0
2: Reserved
3: Down spread MS0
MultiSynth0 Phase Increment/Decrement Control.
0: No phase inc/dec on MS0
1: Enable pin control of phase inc/dec
2: Phase increment on MS0, self clearing
3: Phase decrement on MS0, self clearing
Rev. 0.6
73