SI5338 Datasheet, PDF (72/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
Register 51.
Bit
D7
D6
D5
D4
D3
Name MS3_HS MS2_HS MS1_HS MS0_HS
Type
R/W
R/W
R/W
R/W
D2
D1
D0
MS_PEC[2:0]
Reset value = xxxx x111
Bit
Name
Function
MultiSynth3 High Speed Mode.
When this bit is asserted, MultiSynth3 will only accept divide ratios of 4.0 or 6.0. Incre-
7
MS3_HS _{ment/decrement, SSC, and all phase functions are not available when this bit is set.}
0: MultiSynth3 implements fractional divide ratios between 8 and 1023
1: MultiSynth3 can only implement 4.0 or 6.0 divide ratio.
MultiSynth2 High Speed Mode.
When this bit is asserted, MultiSynth2 will only accept divide ratios of 4.0 or 6.0. Incre-
6
MS2_HS _{ment/decrement, SSC, and all phase functions are not available when this bit is set.}
0: MultiSynth2 implements fractional divide ratios between 8 and 1023.
1: MultiSynth2 can only implement 4.0 or 6.0 divide ratio.
MultiSynth1 High Speed Mode.
When this bit is asserted, MultiSynth1 will only accept divide ratios of 4.0 or 6.0. Incre-
5
MS1_HS _{ment/decrement, SSC, and all phase functions are not available when this bit is set.}
0: MultiSynth1 implements fractional divide ratios between 8 and 1023.
1: MultiSynth1 can only implement 4.0 or 6.0 divide ratio.
MultiSynth0 High Speed Mode.
When this bit is asserted, MultiSynth0 will only accept divide ratios of 4.0 or 6.0. Incre-
4
MS0_HS _{ment/decrement, SSC, and all phase functions are not available when this bit is set.}
0: MultiSynth0 implements fractional divide ratios between 8 and 1023.
1: MultiSynth0 can only implement 4.0 or 6.0 divide ratio.
3
Unused Unused.
MultiSynth Phase Error Correction.
2:0 MS_PEC[2:0]
All non-factory programmed devices must have 111b written to these bits.
72
Rev. 0.6