SI5338 Datasheet, PDF (19/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
3.4. Output Stage
The output stage consists of output selectors, output
dividers, and programmable output drivers as shown in
Figure 7.
Output
Stage
÷R0
÷R1
÷R2
÷R3
VDDO0
CLK0A
CLK0B
VDDO1
CLK1A
CLK1B
VDDO2
CLK2A
CLK2B
VDDO3
CLK3A
CLK3B
Each of the outputs can also be enabled or disabled
through the I²C port. A single pin to enable/disable all
outputs is available in the Si5338K/L/M.
3.5. Configuring the Si5338
The Si5338 is a highly-flexible clock generator that is
entirely configurable through its I²C interface. The
device’s default configuration is stored in non-volatile
memory (NVM) as shown in Figure 8. The NVM is a
one-time programmable memory (OTP), which can
store a custom user configuration at power-up. This is a
useful feature for applications that need a clock present
at power-up (e.g., for providing a clock to a processor).
Power-Up/POR
NVM
(OTP)
Default
Config
RAM
Figure 7. Output Stage
The output selectors select the clock source for the
output drivers. By default, each output driver is
connected to its own MultiSynth block (e.g. M0 to CLK0,
M1 to CLK1, etc), but other combinations are possible
by reconfiguring the device. The PLL can be bypassed
by connected the input stage signals (osc, ref, refdiv, fb,
or fbdiv) directly to the output divider. Bypassing an
input directly to an output will not allow phase alignment
of that output to other outputs. Each of the output
drivers can also connect to the first MultiSynth block
(M0) enabling a fan-out function. This allows the Si5338
to act as a clock generator, a fanout buffer, or a
combination of both in the same package.
The output dividers (R0, R1, R2, R3) allow another
stage of clock division.These dividers are configurable
as divide by 1 (default), 2, 4, 8, 16, or 32. When an Rn
does not equal 1, the phase alignment function for that
output will not work.
The output drivers are configurable to support common
signal formats, such as LVPECL, LVDS, HCSL, CMOS,
HSTL, and SSTL. Separate output supply pins (VDDO_n)
are provided for each output buffer.
The voltage on these supply pins can be 3.3, 2.5, 1.8, or
1.5 V as needed for the possible output formats.
Additionally, the outputs can be configured to stop high,
low, or tri-state when the PLL has lost lock. If the Si5338
is used in a zero delay mode, the output that is fed back
must be set for always on, which will override any
output disable signal.
I²C
Figure 8. Si5338 Memory Configuration
During a power cycle or a power-on reset (POR), the
contents of the NVM are copied into random access
memory (RAM), which sets the device configuration that
will be used during operation. Any changes to the
device configuration after power-up are made by
reading and writing to registers in the RAM space
through the I²C interface. ClockBuilder Desktop (see
"3.1.1. ClockBuilder™ Desktop Software" on page 16)
can be used to easily configure register map files that
can be written into RAM (see “3.5.2. Creating a New
Configuration for RAM” for details). Alternatively, the
register map file can be created manually with the help
of the equations in AN411.
Two versions of the Si5338 are available. First,
standard, non-customized Si5338 devices are available
in which the RAM can be configured in-circuit via I²C
(example part number Si5338C-A-GM). Alternatively,
standard Si5338 devices can be field-programmed
using the Si5338-PROG-EVB field programmer.
Second, custom factory-programmed Si5338 devices
are available that include a user-specified startup
frequency configuration (example part number
Si5338C-Axxxxx-GM).
Rev. 0.6
19