SI5338 Datasheet, PDF (101/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
Register 110.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name CLK0_DISST[1:0]
MS0_PHSTEP[13:8]
Type
R/W
R/W
Reset value = xxxx xxxx
Bit
Name
Function
CLK0 Output Driver State When Disabled.
00: High impedance
7:6
CLK0_DISST[1:0
01: Logic low
10: Logic high
11: Always on even if disabled
MS0 Phase Step Size.
The phase step size is MS0_PHSTEP[13:0]*Tvco/128 where Tvco is
5:0
MS0_PHSTEP[13:8]
the period of the VCO. Either the phase inc/dec pins (if available) or
register 52[1:0] will control the stepping of phase. A phase increment
will delay the clock edge.
Register 111.
Bit
D7
D6
Name
Type
Reset value = xxxx xxxx
Bit
Name
7:0
MS1_PHOFF[7:0]
D5
D4
D3
D2
D1
D0
MS1_PHOFF[7:0]
R/W
Function
MultiSynth1 Initial Phase Offset.
MultiSynth1_PHOFF[14:0] is a 2s complement number. The initial phase
offset is MultiSynth1_PHOFF[14:0]*Tvco/128 where Tvco is the period of
the VCO.
Rev. 0.6
101