SI5338 Datasheet, PDF (16/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
3. Functional Description
IN1
IN2
IN3
IN4
IN5
IN6
SCL
SDA
INTR
VDD
Input
Osc
Stage
Synthesis
Stage 1
(PLL)
CLKIN
÷P1
FDBK
÷P2
ref
Phase
Frequency
Loop
Filter
VCO
Detector
fb
OEB/PINC/FINC
I2C_LSB/PDEC/FDEC
Control & Memory
Control
NVM
(OTP)
RAM
MultiSynth
÷N
Synthesis
Stage 2
MultiSynth
÷M0
MultiSynth
÷M1
MultiSynth
÷M2
MultiSynth
÷M3
Output
Stage
÷R0
÷R1
÷R2
÷R3
VDDO0
CLK0A
CLK0B
VDDO1
CLK1A
CLK1B
VDDO2
CLK2A
CLK2B
VDDO3
CLK3A
CLK3B
Figure 1. Si5338 Block Diagram
3.1. Overview
The Si5338 is a high-performance, low-jitter clock
generator capable of synthesizing four independent
user-programmable clock frequencies up to 350 MHz
and select frequencies up to 710 MHz. The device
supports free-run operation using an external crystal, or
it can lock to an external clock for generating
synchronous clocks. The output drivers support four
differential clocks or eight single-ended clocks or a
combination of both. The output drivers are configurable
to support common signal formats, such as LVPECL,
LVDS, HCSL, CMOS, HSTL, and SSTL. Separate
output supply pins allow supply voltages of 3.3, 2.5, 1.8,
and 1.5 V to support the multi-format output driver. The
core voltage supply accepts 3.3, 2.5, or 1.8 V and is
independent from the output supplies.
Using its two-stage synthesis architecture and patented
high-resolution MultiSynth technology, the Si5338 can
generate four independent frequencies from a single
input frequency. In addition to clock generation, the
inputs can bypass the synthesis stage enabling the
Si5338 to be used as a high-performance clock buffer or
a combination of a buffer and generator.
For applications that need fine frequency adjustments,
such as clock margining, each of the synthesized
frequencies can be incremented or decremented in
user-defined steps as low as 1 ppm per step.
Output-to-output phase delays are also adjustable in
user-defined steps with an error of <20 ps to
compensate for PCB trace delays or for fine tuning of
setup and hold margins.
A zero-delay mode is also available to help minimize
input-to-output delay. Spread spectrum is available on
each of the clock outputs for EMI-sensitive applications,
such as PCI Express.
Configuration and control of the Si5338 is mainly
handled through the I²C/SMBus interface. Some
features, such as output enable and frequency or phase
adjustments, can optionally be pin controlled. The
device has a maskable interrupt pin that can be
monitored for loss of lock or loss of input signal
conditions.
The device also provides the option of storing a user-
definable clock configuration in its non-volatile memory
(NVM), which becomes the default clock configuration
at power-up.
3.1.1. ClockBuilder™ Desktop Software
To simplify device configuration, Silicon Labs provides
ClockBuilder Desktop software. To ease these steps,
Silicon Labs has released ClockBuilder Desktop. The
software serves two purposes: configure the Si5338
with optimal divider ratios based on the desired
frequencies, and to control the EVB, if connected to the
host PC. The optimal configuration can be saved from
the software in text files that can be used in any system,
which configures the device over I²C.
ClockBuilder Desktop can be downloaded from
www.silabs.com/ClockBuilder and runs on Windows XP,
Windows Vista, and Windows 7.
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Rev. 0.6