SI5338 Datasheet, PDF (67/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
Register 39.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
DRV3_INV[1:0]
DRV3_FMT[2:0]
Type
R/W
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:5
Reserved
Reserved.
Invert Driver for CLK3 for CMOS/SSTL/HSTL Outputs.
0: Both outputs are in phase
4:3
DRV3_INV[1:0] 1: CLK3A inverted
2: CLK3B inverted
3: CLK3A/B inverted and in phase
CLK3 Signal Format.
0: Reserved
1: CLK3A = (CMOS/SSTL/HSTL), CLK3B = off
2: CLK3B = (CMOS/SSTL/HSTL), CLK3A = off
2:0 DRV3_FMT[2:0] 3: CLK3A,B = (CMOS/SSTL/HSTL)
4: LVPECL
5: Reserved
6: LVDS
7: HCSL
Register 40.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
DRV1_TRIM [2:0]
DRV0_TRIM [4:0]
Type
R/W
R/W
Reset value = xxxx xxxx
Bit
Name
Function
Trim Bits for CLK1 Driver.
7:5 DRV1_TRIM [2:0] Clockbuilder Desktop sets these values automatically. See AN411 for required
manual settings information
Trim Bits for CLK0 Driver.
4:3 DRV0_TRIM [4:0] _{Clockbuilder Desktop sets these values automatically. See AN411 for required}
manual settings information
Rev. 0.6
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