SI5338 Datasheet, PDF (79/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
Register 63.
Bit D7
Name
Type
D6
D5
MS1_FIDCT[1:0]
R/W
Reset value = xxxx xxxx
Bit
Name
7
Reserved
6:5
MS1_FIDCT[1:0]
4
MS1_FIDDIS
3:2
MS1_SSMODE[1:0]
1:0
MS1_PHIDCT[1:0]
D4
MS1_FIDDIS
R/W
D3
D2
MS1_SSMODE[1:0]
R/W
D1
D0
MS1_PHIDCT[1:0]
R/W
Function
Reserved.
MultiSynth1 Frequency Increment/Decrement Control.
Bit 4 (disable) must be 0 before writing an increment or decrement
to these bits.
0: No frequency inc/dec on MS1
1: Reserved
2: Frequency increment on MS1, self-clearing
3: Frequency decrement on MS1, self-clearing
MultiSynth1 Frequency Increment/Decrement Disable.
See also Register 242[1].
0: Frequency inc/dec enabled on MS1
1: Frequency inc/dec disabled on MS1
MultiSynth1 Spread Spectrum Mode Select.
0: No SSC on MS1
1: Center spread on MS1
2: Reserved
3: Downspread MS1
MultiSynth1 Phase Increment/Decrement Control.
Writing a 10 or 11 will self clear back to 0.
0: No phase inc/dec on MS1
1: Enable pin control of phase inc/dec
2: Phase increment on MS1, self clearing
3: Phase decrement on MS1, self clearing
Rev. 0.6
79