SI5338 Datasheet, PDF (8/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
Table 6. Input and Output Clock Characteristics (Continued)
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Input Impedance
R_IN
10
—
—
Input Capacitance
C_IN
—
3.5
—
Input Clock (DC-Coupled Single-Ended Input Clock on Pins IN3/4)
Frequency
f_IN
Input Voltage
V_I
Input Voltage Swing
CMOS
200 MHz
5
—
200
–0.1
—
3.63
0.8
—
VDD+10%
Rise/Fall Time
Duty Cycle^2,3
t_R/t_F
20%–80%
DC
< 4 ns tr/tf
—
—
2
40
—
60
Input Capacitance
C_IN
Output Clocks (Differential)
—
2.0
—
0.16
—
350
Frequency⁴
LVPECL, LVDS
367
f_OUT
550
—
473.33
—
710
HCSL
0.16
—
250
LVPECL Output Voltage
V_OC
V_SEPP
common mode
peak-to-peak single-
ended swing
—
0.55
V_DDO–1.45 V
0.8
—
0.96
LVDS Output Voltage
(2.5/3.3 V)
V_OC
V_SEPP
common mode
peak-to-peak single-
ended swing
1.125
0.25
1.2
0.35
1.275
0.45
V_OC
common mode
0.8
LVDS Output Voltage
(1.8 V)
V_SEPP
peak-to-peak single-
ended swing
0.25
0.875
0.35
0.95
0.45
HCSL Output Voltage
V_OC
V_SEPP
common mode
peak-to-peak single-
ended swing
0.35
0.575
0.375
0.725
0.400
0.85
Rise/Fall Time
Duty Cycle²
t_R/t_F
20%–80%
DC
—
—
450
45
—
55
Notes:
1. For best jitter performance, keep the input slew rate on pins 1,2,5,6 faster than 0.3 V/ns
2. Not in PLL bypass mode.
3. For best jitter performance, keep the input single ended slew rate on pins 3 or 4 faster than 1 V/ns
4. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6.
5. Includes effect of internal series 22  resistor.
Units
k
pF
MHz
V
Vpp
ns
%
pF
MHz
MHz
MHz
MHz
V
V_PP
V
V_PP
V
V_PP
V
V_PP
ps
%
8
Rev. 0.6