SI5338 Datasheet, PDF (46/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
6.3. Register Summary
Table 16. Register Summary
Register
7
6
5
4
3
2
1
0
0
REVID[2:0]
6
PLL_LOL_
MASK
LOS_FDBK_ LOS_CLKIN_
MASK
MASK
SYS_CAL_
MASK
27
I2C_1P8_SEL
I2C_ADDR[6:0]
28
FDBK_PDN
P2DIV_IN[0]
P1DIV_IN[2:0]
XTAL_FREQ[1:0]
29
PFD_IN_REF[2:0]
P1DIV_IN[4:3]
P1DIV[2:0]
30
PFD_IN_FB[2:0]
P2DIV_IN[2:1]
P2DIV[2:0]
31
R0DIV_IN[2:0]
R0DIV[2:0]
MS0_PDN DRV0_PDN
32
R1DIV_IN[2:0]
R1DIV[2:0]
MS1_PDN DRV1_PDN
33
R2DIV_IN[2:0]
R2DIV[2:0]
MS2_PDN DRV2_PDN
34
R3DIV_IN[2:0]
R3DIV[2:0]
MS3_PDN DRV3_PDN
35
DRV3_VDDO[1:0]
DRV2_VDDO[1:0]
DRV1_VDDO[1:0]
DRV0_VDDO[1:0]
36
DRV0_INV[1:0]
DRV0_FMT[2:0]
37
DRV1_INV[1:0]
DRV1_FMT[2:0]
38
DRV2_INV[1:0]
DRV2_FMT[2:0]
39
DRV3_INV[1:0]
DRV3_FMT[2:0]
40
DRV1_TRIM[2:0]
DRV0_TRIM[4:0]
41
DRV2_TRIM[4:0]
DRV1_TRIM[4:3]
42
DRV3_TRIM[4:0]
45
FCAL_OVRD[7:0]
46
FCAL_OVRD[15:8]
47
FCAL_OVRD[17:16]
48
PFD_EXTFB
PLL_KPHI[6:0]
49 FCAL_OVRD_EN
VCO_GAIN[2:0]
RSEL[1:0]
BWSEL[1:0]
50
PLL_ENABLE[1:0]
MSCAL[5:0]
51
MS3_HS
MS2_HS MS1_HS
MS0_HS
MS_PEC[2:0]
52
MS0_FIDCT[1:0]
MS0_FIDDIS
MS0_SSMODE[1:0]
MS0_PHIDCT[1:0]
53
MS0_P1[7:0]
54
MS0_P1[15:8]
55
MS0_P2[5:0]
MS0_P1[17:16]
56
MS0_P2[13:6]
57
MS0_P2[21:14]
58
MS0_P2[29:22]
59
MS0_P3[7:0]
46
Rev. 0.6