SI5338 Datasheet, PDF (27/170 Pages) Silicon Laboratories – I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5338
5. I²C Interface
Configuration and operation of the Si5338 is controlled
by reading and writing to the RAM space using the I²C
interface. The device operates in slave mode with 7-bit
addressing and can operate in Standard-Mode
(100 kbps) or Fast-Mode (400 kbps) and supports burst
data transfer with auto address increments.
The I²C bus consists of a bidirectional serial data line
(SDA) and a serial clock input (SCL) as shown in
Figure 20. Both the SDA and SCL pins must be
connected to the VDD supply via an external pull-up as
recommended by the I²C specification.
I²C Bus
VDD
I2C_LSB
0/1
SCL
SDA
OEB/PINC/FINC
I2C_LSB/PDEC/FDEC
Control
Figure 20. I²C and Control Signals
The 7-bit device (slave) address of the Si5338 consists
of a 6-bit fixed address plus a user-selectable LSB bit as
shown in Figure 21. The LSB bit is selectable using the
optional I2C_LSB pin which is available as an ordering
option for applications that require more than one
Si5338 on a single I²C bus. Devices without the
I2C_LSB pin option have a fixed 7-bit address of 70h
(111 0000) as shown in Figure 21. Other custom I²C
addresses are also possible. See Table 18 for details on
device ordering information with the optional I2C_LSB
pin.
Write Operation – Single Byte
S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A P
Write Operation - Burst (Auto Address Increment)
S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A Data [7:0] A P
Reg Addr +1
From slave to master
From master to slave
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
Figure 22. I²C Write Operation
A read operation is performed in two stages. A data
write is used to set the register address, then a data
read is performed to retrieve the data from the set
address. A read burst operation is also supported. This
is shown in Figure 23.
Read Operation – Single Byte
S Slv Addr [6:0] 0 A Reg Addr [7:0] A P
S Slv Addr [6:0] 1 A Data [7:0] N P
Read Operation - Burst (Auto Address Increment)
S Slv Addr [6:0] 0 A Reg Addr [7:0] A P
S Slv Addr [6:0] 1 A Data [7:0] A Data [7:0] N P
Reg Addr +1
Slave Address
(with I2C_LSB Option)
6 54 32 1 0
1 1 1 0 0 0 0/1
I2C_LSB pin
Slave Address
(without I2C_LSB Option)
6 54 32 1 0
111000 0
From slave to master
From master to slave
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
Figure 23. I²C Read Operation
Figure 21. Si5338 I²C Slave Address
Data is transferred MSB first in 8-bit words as specified
by the I²C specification. A write command consists of a
7-bit device (slave) address + a write bit, an 8-bit
register address, and 8 bits of data as shown in
Figure 22. A write burst operation is also shown where
every additional data word is written using an auto-
incremented address.
AC and DC electrical specifications for the SCL and
SDA pins are shown in Table 14. The timing
specifications and timing diagram for the I²C bus are
compatible with the I²C-Bus Standard. SDA timeout is
supported for compatibility with SMBus interfaces.
The I²C bus can be operated at a bus voltage of 1.71 to
3.63 V and is 3.3 V tolerant. If a bus voltage of less than
2.5 V is used, register 27[7] = 1 must be written to
maintain compatibility with the I²C bus standard.
Rev. 0.6
27